[PATCH] D27916: [RFC]Make the canonicalisation on shifts benifit to more case.

[jojo.ma via Phabricator via llvm-commits]

jojo created this revision.
jojo added reviewers: efriedma, eli.friedman, evstupac, jmolloy, rengolin.
jojo added subscribers: llvm-commits, test.

Do canonicalisation on cases similar to below also profitable,
except on cases in "shift-or/xor/and/add-shift" context.

define i32 @test(i32 %v) {
entry:

  %a = and i32 %v, 65534
  %b = lshr i32 %a, 1
  %c = and i32 %v, 65535
  %d = lshr i32 %c, 1
  %e = add i32 %b, %d
  ret i32 %e

}


https://reviews.llvm.org/D27916

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4550,10 +4550,17 @@
   //    void foo(int *X, int i) { X[i & 1235] = 1; }
   //    int bar(int *X, int i) { return X[i & 255]; }
   SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
-  if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
+  if (((BinOpLHSVal->getOpcode() != ISD::SHL &&
        BinOpLHSVal->getOpcode() != ISD::SRA &&
        BinOpLHSVal->getOpcode() != ISD::SRL) ||
-      !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
+      !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) &&
+       BinOpLHSVal->getOpcode() != ISD::CopyFromReg &&
+       BinOpLHSVal->getOpcode() != ISD::SELECT)
+    return SDValue();
+
+  if ((BinOpLHSVal->getOpcode() == ISD::CopyFromReg ||
+       BinOpLHSVal->getOpcode() == ISD::SELECT) &&
+       N->hasOneUse())
     return SDValue();
 
   EVT VT = N->getValueType(0);


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