[PATCH] D27910: [ARM] ARMLoadStoreOpt generates deprecated T1 STM

[Z. Zheng via Phabricator via llvm-commits]

zzheng created this revision.
zzheng added reviewers: t.p.northover, jmolloy, zinob, efriedma, apazos.
zzheng added a subscriber: llvm-commits.
zzheng set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.

Fix for

if (isThumb1 && isi32Load && ...) {

  if (...)
  else if (opcode == ARM:tSTRi) 
     ... 

}

and add an test case. This would prevent generating stm r1!, {r1, r0} on Thumb1, where value stored for r1 is UNKONWN.


Repository:
  rL LLVM

https://reviews.llvm.org/D27910

Files:
  lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  test/CodeGen/Thumb/stm-deprecated.ll


Index: test/CodeGen/Thumb/stm-deprecated.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Thumb/stm-deprecated.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv5e-linux-gnueabi -verify-machineinstrs %s -o - | FileCheck %s
+
+%0 = type { %0*, %0*, i32 }
+
+ at x1 = external global %0, align 4
+ at x2 = external global %0, align 4
+
+; CHECK: str r1, [r0, #8]
+; CHECK: str r0, [r1]
+; CHECK-NEXT: str r1, [r1, #4]
+; CHECK-NOT: stm
+
+define void @foo() {
+  store i32 3, i32* getelementptr inbounds (%0, %0* @x1, i32 0, i32 2)
+  store %0* @x1, %0** getelementptr inbounds (%0, %0* @x2, i32 0, i32 0)
+  store %0* @x2, %0** getelementptr inbounds (%0, %0* @x2, i32 0, i32 1)
+  unreachable
+}
Index: lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -602,13 +602,12 @@
   // Exception: If the base register is in the input reglist, Thumb1 LDM is
   // non-writeback.
   // It's also not possible to merge an STR of the base register in Thumb1.
-  if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
+  if (isThumb1 && ContainsReg(Regs, Base)) {
     assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
-    if (Opcode == ARM::tLDRi) {
+    if (Opcode == ARM::tLDRi)
       Writeback = false;
-    } else if (Opcode == ARM::tSTRi) {
+    else if (Opcode == ARM::tSTRi)
       return nullptr;
-    }
   }
 
   ARM_AM::AMSubMode Mode = ARM_AM::ia;


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