[PATCH] D27901: [X86][[AVX512] Code size reduction in X86 by replacing EVEX with VEX encoding

Gadi Haber via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 18 07:09:02 PST 2016


gadi.haber created this revision.
gadi.haber added reviewers: zvi, delena, craig.topper, igorb.
gadi.haber added a subscriber: llvm-commits.
gadi.haber set the repository for this revision to rL LLVM.
Herald added a subscriber: mgorny.

This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible.

There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers.
The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled.

For example: “vmovss  %xmm0, 32(%rsp,%rax,4)“, has the following 2 possible encodings:

EVEX encoding (8 bytes long):

  62 f1 7e 08 11 44 84 08         vmovss  %xmm0, 32(%rsp,%rax,4)

VEX encoding (6 bytes long):

  c5 fa 11 44 84 20                     vmovss  %xmm0, 32(%rsp,%rax,4)

Reported Bugzilla bugs related to this patch:
https://llvm.org/bugs/show_bug.cgi?id=23376
https://llvm.org/bugs/show_bug.cgi?id=29162

In this patch we created a new pass called createX86EvexToVexInsts at the pre-emit stage which uses a table of all EVEX opcodes that can be encoded via VEX.
The table is placed in a separate header file along with the above pass file under lib/Target/X86.

The patch requires many modifications to CodeGen/X86 unit tests since a new  string: "EVEX TO VEX Compression " was added to the encoding string of each optimized instruction. The string is printed whenever the llc --show-mc-encoding flag is applied.
Finally, an additional MIR test file was added to the  CodeGen/X86 unit tests called: "evex-to-vex.mir" containing all the EVEX instructions that are handled by this optimization.


Repository:
  rL LLVM

https://reviews.llvm.org/D27901

Files:
  include/llvm/MC/MCStreamer.h
  lib/MC/MCAsmStreamer.cpp
  lib/Target/X86/CMakeLists.txt
  lib/Target/X86/InstPrinter/X86InstComments.h
  lib/Target/X86/X86.h
  lib/Target/X86/X86EvexToVex.cpp
  lib/Target/X86/X86InstrTablesInfo.h
  lib/Target/X86/X86MCInstLower.cpp
  lib/Target/X86/X86TargetMachine.cpp
  test/CodeGen/X86/avx-intrinsics-x86.ll
  test/CodeGen/X86/avx2-intrinsics-x86.ll
  test/CodeGen/X86/avx2-vbroadcast.ll
  test/CodeGen/X86/avx512-arith.ll
  test/CodeGen/X86/avx512-cvt.ll
  test/CodeGen/X86/avx512-ext.ll
  test/CodeGen/X86/avx512-gather-scatter-intrin.ll
  test/CodeGen/X86/avx512-mask-op.ll
  test/CodeGen/X86/avx512-masked_memop-16-8.ll
  test/CodeGen/X86/avx512-mov.ll
  test/CodeGen/X86/avx512-scalar.ll
  test/CodeGen/X86/avx512-vbroadcasti128.ll
  test/CodeGen/X86/avx512-vbroadcasti256.ll
  test/CodeGen/X86/avx512-vec-cmp.ll
  test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
  test/CodeGen/X86/avx512bwvl-intrinsics.ll
  test/CodeGen/X86/avx512bwvl-mov.ll
  test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll
  test/CodeGen/X86/avx512dqvl-intrinsics.ll
  test/CodeGen/X86/avx512ifmavl-intrinsics.ll
  test/CodeGen/X86/avx512vbmivl-intrinsics.ll
  test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
  test/CodeGen/X86/avx512vl-intrinsics.ll
  test/CodeGen/X86/avx512vl-logic.ll
  test/CodeGen/X86/avx512vl-mov.ll
  test/CodeGen/X86/avx512vl-nontemporal.ll
  test/CodeGen/X86/avx512vl-vbroadcast.ll
  test/CodeGen/X86/compress_expand.ll
  test/CodeGen/X86/evex-to-vex-compress.mir
  test/CodeGen/X86/fast-isel-store.ll
  test/CodeGen/X86/masked_gather_scatter.ll
  test/CodeGen/X86/masked_memop.ll
  test/CodeGen/X86/nontemporal-2.ll
  test/CodeGen/X86/sse-intrinsics-x86.ll
  test/CodeGen/X86/sse2-intrinsics-x86.ll
  test/CodeGen/X86/sse41-intrinsics-x86.ll
  test/CodeGen/X86/sse42-intrinsics-x86.ll
  test/CodeGen/X86/ssse3-intrinsics-x86.ll
  test/CodeGen/X86/subvector-broadcast.ll
  test/CodeGen/X86/vec_fp_to_int.ll
  test/CodeGen/X86/vec_fpext.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-half-conversions.ll
  test/CodeGen/X86/vector-lzcnt-256.ll
  test/CodeGen/X86/vector-shuffle-128-v16.ll
  test/CodeGen/X86/vector-shuffle-128-v2.ll
  test/CodeGen/X86/vector-shuffle-128-v4.ll
  test/CodeGen/X86/vector-shuffle-128-v8.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v32.ll
  test/CodeGen/X86/vector-shuffle-256-v8.ll
  test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
  test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
  test/CodeGen/X86/vector-shuffle-masked.ll
  test/CodeGen/X86/vector-trunc.ll
  test/CodeGen/X86/vector-tzcnt-128.ll
  test/CodeGen/X86/vector-tzcnt-256.ll
  test/CodeGen/X86/viabs.ll

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