[llvm] r290048 - [AVX-512] Update scalar logic test to show missed opportunity to use EVEX encoded logic instructions to get more registers to use.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Dec 17 13:25:55 2016
New Revision: 290048

URL: http://llvm.org/viewvc/llvm-project?rev=290048&view=rev
Log:
[AVX-512] Update scalar logic test to show missed opportunity to use EVEX encoded logic instructions to get more registers to use.

Modified:
    llvm/trunk/test/CodeGen/X86/fp-logic-replace.ll

Modified: llvm/trunk/test/CodeGen/X86/fp-logic-replace.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-logic-replace.ll?rev=290048&r1=290047&r2=290048&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp-logic-replace.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fp-logic-replace.ll Sat Dec 17 13:25:55 2016
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+sse2 | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx  | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq  | FileCheck %s --check-prefix=AVX512DQ
 
 ; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction.
 ; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels
@@ -11,13 +12,18 @@
 define double @FsANDPSrr(double %x, double %y) {
 ; SSE-LABEL: FsANDPSrr:
 ; SSE:       # BB#0:
-; SSE-NEXT:    andps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE-NEXT:    andps %xmm1, %xmm0 # encoding: [0x0f,0x54,0xc1]
+; SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; AVX-LABEL: FsANDPSrr:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    retq
+; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x54,0xc1]
+; AVX-NEXT:    retq # encoding: [0xc3]
+;
+; AVX512DQ-LABEL: FsANDPSrr:
+; AVX512DQ:       # BB#0:
+; AVX512DQ-NEXT:    vandps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x54,0xc1]
+; AVX512DQ-NEXT:    retq # encoding: [0xc3]
 ;
   %bc1 = bitcast double %x to i64
   %bc2 = bitcast double %y to i64
@@ -29,14 +35,19 @@ define double @FsANDPSrr(double %x, doub
 define double @FsANDNPSrr(double %x, double %y) {
 ; SSE-LABEL: FsANDNPSrr:
 ; SSE:       # BB#0:
-; SSE-NEXT:    andnps %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE-NEXT:    andnps %xmm0, %xmm1 # encoding: [0x0f,0x55,0xc8]
+; SSE-NEXT:    movaps %xmm1, %xmm0 # encoding: [0x0f,0x28,0xc1]
+; SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; AVX-LABEL: FsANDNPSrr:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vandnps %xmm0, %xmm1, %xmm0
-; AVX-NEXT:    retq
+; AVX-NEXT:    vandnps %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf0,0x55,0xc0]
+; AVX-NEXT:    retq # encoding: [0xc3]
+;
+; AVX512DQ-LABEL: FsANDNPSrr:
+; AVX512DQ:       # BB#0:
+; AVX512DQ-NEXT:    vandnps %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf0,0x55,0xc0]
+; AVX512DQ-NEXT:    retq # encoding: [0xc3]
 ;
   %bc1 = bitcast double %x to i64
   %bc2 = bitcast double %y to i64
@@ -49,13 +60,18 @@ define double @FsANDNPSrr(double %x, dou
 define double @FsORPSrr(double %x, double %y) {
 ; SSE-LABEL: FsORPSrr:
 ; SSE:       # BB#0:
-; SSE-NEXT:    orps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE-NEXT:    orps %xmm1, %xmm0 # encoding: [0x0f,0x56,0xc1]
+; SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; AVX-LABEL: FsORPSrr:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    retq
+; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x56,0xc1]
+; AVX-NEXT:    retq # encoding: [0xc3]
+;
+; AVX512DQ-LABEL: FsORPSrr:
+; AVX512DQ:       # BB#0:
+; AVX512DQ-NEXT:    vorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x56,0xc1]
+; AVX512DQ-NEXT:    retq # encoding: [0xc3]
 ;
   %bc1 = bitcast double %x to i64
   %bc2 = bitcast double %y to i64
@@ -67,13 +83,18 @@ define double @FsORPSrr(double %x, doubl
 define double @FsXORPSrr(double %x, double %y) {
 ; SSE-LABEL: FsXORPSrr:
 ; SSE:       # BB#0:
-; SSE-NEXT:    xorps %xmm1, %xmm0
-; SSE-NEXT:    retq
+; SSE-NEXT:    xorps %xmm1, %xmm0 # encoding: [0x0f,0x57,0xc1]
+; SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; AVX-LABEL: FsXORPSrr:
 ; AVX:       # BB#0:
-; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    retq
+; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc1]
+; AVX-NEXT:    retq # encoding: [0xc3]
+;
+; AVX512DQ-LABEL: FsXORPSrr:
+; AVX512DQ:       # BB#0:
+; AVX512DQ-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc1]
+; AVX512DQ-NEXT:    retq # encoding: [0xc3]
 ;
   %bc1 = bitcast double %x to i64
   %bc2 = bitcast double %y to i64