[llvm] r290024 - [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
Eugene Zelenko via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 16 17:09:05 PST 2016
Author: eugenezelenko
Date: Fri Dec 16 19:09:05 2016
New Revision: 290024
URL: http://llvm.org/viewvc/llvm-project?rev=290024&view=rev
Log:
[Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/trunk/lib/Target/Hexagon/HexagonStoreWidening.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp Fri Dec 16 19:09:05 2016
@@ -13,12 +13,13 @@
//===----------------------------------------------------------------------===//
#include "HexagonHazardRecognizer.h"
-#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include <cassert>
using namespace llvm;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.h Fri Dec 16 19:09:05 2016
@@ -9,8 +9,8 @@
// This file defines the hazard recognizer for scheduling on Hexagon.
//===----------------------------------------------------------------------===//
-#ifndef HEXAGONPROFITRECOGNIZER_H
-#define HEXAGONPROFITRECOGNIZER_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H
+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
@@ -40,39 +40,39 @@ public:
: Resources(ST.createDFAPacketizer(II)), TII(HII), PacketNum(0),
UsesDotCur(nullptr), DotCurPNum(-1) { }
- ~HexagonHazardRecognizer() {
+ ~HexagonHazardRecognizer() override {
if (Resources)
delete Resources;
}
/// This callback is invoked when a new block of instructions is about to be
/// scheduled. The hazard state is set to an initialized state.
- virtual void Reset() override;
+ void Reset() override;
/// Return the hazard type of emitting this node. There are three
/// possible results. Either:
/// * NoHazard: it is legal to issue this instruction on this cycle.
/// * Hazard: issuing this instruction would stall the machine. If some
/// other instruction is available, issue it first.
- virtual HazardType getHazardType(SUnit *SU, int stalls) override;
+ HazardType getHazardType(SUnit *SU, int stalls) override;
/// This callback is invoked when an instruction is emitted to be scheduled,
/// to advance the hazard state.
- virtual void EmitInstruction(SUnit *) override;
+ void EmitInstruction(SUnit *) override;
/// This callback may be invoked if getHazardType returns NoHazard. If, even
/// though there is no hazard, it would be better to schedule another
/// available instruction, this callback should return true.
- virtual bool ShouldPreferAnother(SUnit *) override;
+ bool ShouldPreferAnother(SUnit *) override;
/// This callback is invoked whenever the next top-down instruction to be
/// scheduled cannot issue in the current cycle, either because of latency
/// or resource conflicts. This should increment the internal state of the
/// hazard recognizer so that previously "Hazard" instructions will now not
/// be hazards.
- virtual void AdvanceCycle() override;
+ void AdvanceCycle() override;
};
} // end namespace llvm
-#endif // HEXAGONPROFITRECOGNIZER_H
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Fri Dec 16 19:09:05 2016
@@ -12,30 +12,52 @@
//
//===----------------------------------------------------------------------===//
+#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonMachineFunctionInfo.h"
+#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonTargetMachine.h"
#include "HexagonTargetObjectFile.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/CallingConv.h"
+#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
-#include "llvm/IR/GlobalAlias.h"
-#include "llvm/IR/GlobalVariable.h"
+#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/InlineAsm.h"
+#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetCallingConv.h"
+#include "llvm/Target/TargetMachine.h"
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <limits>
+#include <utility>
using namespace llvm;
@@ -83,6 +105,7 @@ static cl::opt<int> MaxStoresPerMemsetOp
namespace {
+
class HexagonCCState : public CCState {
unsigned NumNamedVarArgParams;
@@ -101,7 +124,8 @@ namespace {
Odd,
NoPattern
};
-}
+
+} // end anonymous namespace
// Implement calling convention for Hexagon.
@@ -222,7 +246,6 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT V
llvm_unreachable(nullptr);
}
-
static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (ArgFlags.isByVal()) {
@@ -278,7 +301,6 @@ static bool CC_Hexagon (unsigned ValNo,
static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
-
static const MCPhysReg RegList[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5
@@ -296,7 +318,6 @@ static bool CC_Hexagon32(unsigned ValNo,
static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
-
if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
@@ -321,7 +342,6 @@ static bool CC_Hexagon64(unsigned ValNo,
static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
-
static const MCPhysReg VecLstS[] = {
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
@@ -579,7 +599,6 @@ HexagonTargetLowering::LowerReturn(SDVal
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &dl, SelectionDAG &DAG) const {
-
// CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs;
@@ -1084,7 +1103,6 @@ SDValue HexagonTargetLowering::LowerForm
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
-
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
@@ -1405,7 +1423,6 @@ SDValue HexagonTargetLowering::LowerLOAD
return DAG.getMergeValues(Ops, DL);
}
-
SDValue
HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
EVT ValTy = Op.getValueType();
@@ -1493,7 +1510,6 @@ HexagonTargetLowering::LowerATOMIC_FENCE
return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
}
-
SDValue
HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
@@ -1782,7 +1798,6 @@ HexagonTargetLowering::HexagonTargetLowe
addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
}
-
}
//
@@ -1833,7 +1848,7 @@ HexagonTargetLowering::HexagonTargetLowe
if (EmitJumpTables)
setMinimumJumpTableEntries(MinimumJumpTables);
else
- setMinimumJumpTableEntries(INT_MAX);
+ setMinimumJumpTableEntries(std::numeric_limits<int>::max());
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
// Hexagon has instructions for add/sub with carry. The problem with
@@ -2067,7 +2082,6 @@ HexagonTargetLowering::HexagonTargetLowe
setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
-
} else { // V4
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
@@ -2233,7 +2247,6 @@ HexagonTargetLowering::HexagonTargetLowe
setLibcallName(RTLIB::SRA_I128, nullptr);
}
-
const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((HexagonISD::NodeType)Opcode) {
case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
@@ -2441,7 +2454,7 @@ static bool isCommonSplatElement(BuildVe
// <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
SDValue
HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
- BuildVectorSDNode *BVN = 0;
+ BuildVectorSDNode *BVN = nullptr;
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDValue V3;
@@ -3107,7 +3120,6 @@ bool HexagonTargetLowering::isOffsetFold
return HTM.getRelocationModel() == Reloc::Static;
}
-
/// isLegalICmpImmediate - Return true if the specified immediate is legal
/// icmp immediate, that is the target has icmp instructions which can compare
/// a register against the immediate without having to materialize the
@@ -3224,7 +3236,6 @@ bool HexagonTargetLowering::allowsMisali
return false;
}
-
std::pair<const TargetRegisterClass*, uint8_t>
HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Fri Dec 16 19:09:05 2016
@@ -16,12 +16,21 @@
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
#include "Hexagon.h"
-#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
+#include "llvm/IR/InlineAsm.h"
#include "llvm/Target/TargetLowering.h"
+#include <cstdint>
+#include <utility>
namespace llvm {
- namespace HexagonISD {
+
+namespace HexagonISD {
+
enum NodeType : unsigned {
OP_BEGIN = ISD::BUILTIN_OP_END,
@@ -80,18 +89,19 @@ namespace llvm {
OP_END
};
- }
+
+} // end namespace HexagonISD
class HexagonSubtarget;
class HexagonTargetLowering : public TargetLowering {
int VarArgsFrameOffset; // Frame offset to start of varargs area.
+ const HexagonTargetMachine &HTM;
+ const HexagonSubtarget &Subtarget;
bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
const;
void promoteLdStType(MVT VT, MVT PromotedLdStVT);
- const HexagonTargetMachine &HTM;
- const HexagonSubtarget &Subtarget;
public:
explicit HexagonTargetLowering(const TargetMachine &TM,
@@ -199,6 +209,7 @@ namespace llvm {
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
+
EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
EVT VT) const override {
if (!VT.isVector())
@@ -277,6 +288,7 @@ namespace llvm {
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
const override;
};
+
} // end namespace llvm
-#endif // Hexagon_ISELLOWERING_H
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp Fri Dec 16 19:09:05 2016
@@ -9,32 +9,50 @@
#define DEBUG_TYPE "hsdr"
+#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
-#include "HexagonTargetMachine.h"
-
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
-
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <limits>
#include <map>
#include <set>
+#include <utility>
#include <vector>
using namespace llvm;
namespace llvm {
+
FunctionPass *createHexagonSplitDoubleRegs();
void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
-}
+
+} // end namespace llvm
namespace {
+
static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
cl::desc("Maximum number of split partitions"));
static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
@@ -43,18 +61,22 @@ namespace {
class HexagonSplitDoubleRegs : public MachineFunctionPass {
public:
static char ID;
+
HexagonSplitDoubleRegs() : MachineFunctionPass(ID), TRI(nullptr),
TII(nullptr) {
initializeHexagonSplitDoubleRegsPass(*PassRegistry::getPassRegistry());
}
+
StringRef getPassName() const override {
return "Hexagon Split Double Registers";
}
+
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
+
bool runOnMachineFunction(MachineFunction &MF) override;
private:
@@ -98,16 +120,17 @@ namespace {
static void dump_partition(raw_ostream&, const USet&,
const TargetRegisterInfo&);
};
+
char HexagonSplitDoubleRegs::ID;
int HexagonSplitDoubleRegs::Counter = 0;
const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC
= &Hexagon::DoubleRegsRegClass;
-}
+
+} // end anonymous namespace
INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
"Hexagon Split Double Registers", false, false)
-
void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
const USet &Part, const TargetRegisterInfo &TRI) {
dbgs() << '{';
@@ -116,7 +139,6 @@ void HexagonSplitDoubleRegs::dump_partit
dbgs() << " }";
}
-
bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
for (auto I : IRM) {
const USet &Rs = I.second;
@@ -126,7 +148,6 @@ bool HexagonSplitDoubleRegs::isInduction
return false;
}
-
bool HexagonSplitDoubleRegs::isVolatileInstr(const MachineInstr *MI) const {
for (auto &I : MI->memoperands())
if (I->isVolatile())
@@ -134,7 +155,6 @@ bool HexagonSplitDoubleRegs::isVolatileI
return false;
}
-
bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
if (MI->mayLoad() || MI->mayStore())
if (MemRefsFixed || isVolatileInstr(MI))
@@ -194,7 +214,6 @@ bool HexagonSplitDoubleRegs::isFixedInst
return false;
}
-
void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
typedef std::map<unsigned,unsigned> UUMap;
typedef std::vector<unsigned> UVect;
@@ -283,7 +302,6 @@ void HexagonSplitDoubleRegs::partitionRe
P2Rs[I.second].insert(I.first);
}
-
static inline int32_t profitImm(unsigned Lo, unsigned Hi) {
int32_t P = 0;
bool LoZ1 = false, HiZ1 = false;
@@ -296,7 +314,6 @@ static inline int32_t profitImm(unsigned
return P;
}
-
int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
unsigned ImmX = 0;
unsigned Opc = MI->getOpcode();
@@ -372,7 +389,6 @@ int32_t HexagonSplitDoubleRegs::profit(c
return 0;
}
-
bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
const {
unsigned FixedNum = 0, SplitNum = 0, LoopPhiNum = 0;
@@ -381,7 +397,7 @@ bool HexagonSplitDoubleRegs::isProfitabl
for (unsigned DR : Part) {
MachineInstr *DefI = MRI->getVRegDef(DR);
int32_t P = profit(DefI);
- if (P == INT_MIN)
+ if (P == std::numeric_limits<int>::max())
return false;
TotalP += P;
// Reduce the profitability of splitting induction registers.
@@ -414,7 +430,7 @@ bool HexagonSplitDoubleRegs::isProfitabl
// Splittable instruction.
SplitNum++;
int32_t P = profit(UseI);
- if (P == INT_MIN)
+ if (P == std::numeric_limits<int>::max())
return false;
TotalP += P;
}
@@ -427,7 +443,6 @@ bool HexagonSplitDoubleRegs::isProfitabl
return TotalP > 0;
}
-
void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
USet &Rs) {
const MachineBasicBlock *HB = L->getHeader();
@@ -437,7 +452,7 @@ void HexagonSplitDoubleRegs::collectIndR
// Examine the latch branch. Expect it to be a conditional branch to
// the header (either "br-cond header" or "br-cond exit; br header").
- MachineBasicBlock *TB = 0, *FB = 0;
+ MachineBasicBlock *TB = nullptr, *FB = nullptr;
MachineBasicBlock *TmpLB = const_cast<MachineBasicBlock*>(LB);
SmallVector<MachineOperand,2> Cond;
bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false);
@@ -511,7 +526,7 @@ void HexagonSplitDoubleRegs::collectIndR
}
return true;
};
- UVect::iterator End = remove_if(DP, NoIndOp);
+ UVect::iterator End = llvm::remove_if(DP, NoIndOp);
Rs.insert(DP.begin(), End);
Rs.insert(CmpR1);
Rs.insert(CmpR2);
@@ -523,7 +538,6 @@ void HexagonSplitDoubleRegs::collectIndR
});
}
-
void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
typedef std::vector<MachineLoop*> LoopVector;
LoopVector WorkQ;
@@ -545,7 +559,6 @@ void HexagonSplitDoubleRegs::collectIndR
}
}
-
void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
const UUPairMap &PairMap, unsigned SubR) {
MachineBasicBlock &B = *MI->getParent();
@@ -580,7 +593,6 @@ void HexagonSplitDoubleRegs::createHalfI
}
}
-
void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
const UUPairMap &PairMap) {
bool Load = MI->mayLoad();
@@ -653,7 +665,6 @@ void HexagonSplitDoubleRegs::splitMemRef
}
}
-
void HexagonSplitDoubleRegs::splitImmediate(MachineInstr *MI,
const UUPairMap &PairMap) {
MachineOperand &Op0 = MI->getOperand(0);
@@ -681,7 +692,6 @@ void HexagonSplitDoubleRegs::splitImmedi
.addImm(int32_t(V >> 32));
}
-
void HexagonSplitDoubleRegs::splitCombine(MachineInstr *MI,
const UUPairMap &PairMap) {
MachineOperand &Op0 = MI->getOperand(0);
@@ -714,7 +724,6 @@ void HexagonSplitDoubleRegs::splitCombin
llvm_unreachable("Unexpected operand");
}
-
void HexagonSplitDoubleRegs::splitExt(MachineInstr *MI,
const UUPairMap &PairMap) {
MachineOperand &Op0 = MI->getOperand(0);
@@ -735,9 +744,10 @@ void HexagonSplitDoubleRegs::splitExt(Ma
.addImm(31);
}
-
void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
const UUPairMap &PairMap) {
+ using namespace Hexagon;
+
MachineOperand &Op0 = MI->getOperand(0);
MachineOperand &Op1 = MI->getOperand(1);
MachineOperand &Op2 = MI->getOperand(2);
@@ -751,7 +761,6 @@ void HexagonSplitDoubleRegs::splitShift(
const UUPair &P = F->second;
unsigned LoR = P.first;
unsigned HiR = P.second;
- using namespace Hexagon;
unsigned Opc = MI->getOpcode();
bool Right = (Opc == S2_lsr_i_p || Opc == S2_asr_i_p);
@@ -859,9 +868,10 @@ void HexagonSplitDoubleRegs::splitShift(
}
}
-
void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
const UUPairMap &PairMap) {
+ using namespace Hexagon;
+
MachineOperand &Op0 = MI->getOperand(0);
MachineOperand &Op1 = MI->getOperand(1);
MachineOperand &Op2 = MI->getOperand(2);
@@ -876,7 +886,6 @@ void HexagonSplitDoubleRegs::splitAslOr(
const UUPair &P = F->second;
unsigned LoR = P.first;
unsigned HiR = P.second;
- using namespace Hexagon;
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
@@ -952,13 +961,13 @@ void HexagonSplitDoubleRegs::splitAslOr(
}
}
-
bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI,
const UUPairMap &PairMap) {
+ using namespace Hexagon;
+
DEBUG(dbgs() << "Splitting: " << *MI);
bool Split = false;
unsigned Opc = MI->getOpcode();
- using namespace Hexagon;
switch (Opc) {
case TargetOpcode::PHI:
@@ -1035,7 +1044,6 @@ bool HexagonSplitDoubleRegs::splitInstr(
return Split;
}
-
void HexagonSplitDoubleRegs::replaceSubregUses(MachineInstr *MI,
const UUPairMap &PairMap) {
for (auto &Op : MI->operands()) {
@@ -1058,7 +1066,6 @@ void HexagonSplitDoubleRegs::replaceSubr
}
}
-
void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
const UUPairMap &PairMap) {
MachineBasicBlock &B = *MI->getParent();
@@ -1086,7 +1093,6 @@ void HexagonSplitDoubleRegs::collapseReg
}
}
-
bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
typedef std::set<MachineInstr*> MISet;
@@ -1147,7 +1153,6 @@ bool HexagonSplitDoubleRegs::splitPartit
return Changed;
}
-
bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "Splitting double registers in function: "
<< MF.getName() << '\n');
Modified: llvm/trunk/lib/Target/Hexagon/HexagonStoreWidening.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonStoreWidening.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonStoreWidening.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonStoreWidening.cpp Fri Dec 16 19:09:05 2016
@@ -23,33 +23,45 @@
#define DEBUG_TYPE "hexagon-widen-stores"
-#include "HexagonTargetMachine.h"
-
-#include "llvm/PassSupport.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/Analysis/MemoryLocation.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetInstrInfo.h"
-
#include <algorithm>
-
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <vector>
using namespace llvm;
namespace llvm {
+
FunctionPass *createHexagonStoreWidening();
void initializeHexagonStoreWideningPass(PassRegistry&);
-}
+
+} // end namespace llvm
namespace {
+
struct HexagonStoreWidening : public MachineFunctionPass {
const HexagonInstrInfo *TII;
const HexagonRegisterInfo *TRI;
@@ -59,6 +71,7 @@ namespace {
public:
static char ID;
+
HexagonStoreWidening() : MachineFunctionPass(ID) {
initializeHexagonStoreWideningPass(*PassRegistry::getPassRegistry());
}
@@ -96,19 +109,18 @@ namespace {
bool storesAreAdjacent(const MachineInstr *S1, const MachineInstr *S2);
};
-} // namespace
-
+char HexagonStoreWidening::ID = 0;
-namespace {
+} // end anonymous namespace
// Some local helper functions...
-unsigned getBaseAddressRegister(const MachineInstr *MI) {
+static unsigned getBaseAddressRegister(const MachineInstr *MI) {
const MachineOperand &MO = MI->getOperand(0);
assert(MO.isReg() && "Expecting register operand");
return MO.getReg();
}
-int64_t getStoreOffset(const MachineInstr *MI) {
+static int64_t getStoreOffset(const MachineInstr *MI) {
unsigned OpC = MI->getOpcode();
assert(HexagonStoreWidening::handledStoreType(MI) && "Unhandled opcode");
@@ -126,23 +138,17 @@ int64_t getStoreOffset(const MachineInst
return 0;
}
-const MachineMemOperand &getStoreTarget(const MachineInstr *MI) {
+static const MachineMemOperand &getStoreTarget(const MachineInstr *MI) {
assert(!MI->memoperands_empty() && "Expecting memory operands");
return **MI->memoperands_begin();
}
-} // namespace
-
-
-char HexagonStoreWidening::ID = 0;
-
INITIALIZE_PASS_BEGIN(HexagonStoreWidening, "hexagon-widen-stores",
"Hexason Store Widening", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(HexagonStoreWidening, "hexagon-widen-stores",
"Hexagon Store Widening", false, false)
-
// Filtering function: any stores whose opcodes are not "approved" of by
// this function will not be subjected to widening.
inline bool HexagonStoreWidening::handledStoreType(const MachineInstr *MI) {
@@ -160,7 +166,6 @@ inline bool HexagonStoreWidening::handle
}
}
-
// Check if the machine memory operand MMO is aliased with any of the
// stores in the store group Stores.
bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
@@ -183,7 +188,6 @@ bool HexagonStoreWidening::instrAliased(
return false;
}
-
// Check if the machine instruction MI accesses any storage aliased with
// any store in the group Stores.
bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
@@ -194,7 +198,6 @@ bool HexagonStoreWidening::instrAliased(
return false;
}
-
// Inspect a machine basic block, and generate store groups out of stores
// encountered in the block.
//
@@ -231,7 +234,6 @@ void HexagonStoreWidening::createStoreGr
}
}
-
// Create a single store group. The stores need to be independent between
// themselves, and also there cannot be other instructions between them
// that could read or modify storage being stored into.
@@ -261,7 +263,7 @@ void HexagonStoreWidening::createStoreGr
unsigned BR = getBaseAddressRegister(MI);
if (BR == BaseReg) {
Group.push_back(MI);
- *I = 0;
+ *I = nullptr;
continue;
}
}
@@ -278,7 +280,6 @@ void HexagonStoreWidening::createStoreGr
} // for
}
-
// Check if store instructions S1 and S2 are adjacent. More precisely,
// S2 has to access memory immediately following that accessed by S1.
bool HexagonStoreWidening::storesAreAdjacent(const MachineInstr *S1,
@@ -296,7 +297,6 @@ bool HexagonStoreWidening::storesAreAdja
: int(Off1+S1MO.getSize()) == Off2;
}
-
/// Given a sequence of adjacent stores, and a maximum size of a single wide
/// store, pick a group of stores that can be replaced by a single store
/// of size not exceeding MaxSize. The selected sequence will be recorded
@@ -388,7 +388,6 @@ bool HexagonStoreWidening::selectStores(
return true;
}
-
/// Given an "old group" OG of stores, create a "new group" NG of instructions
/// to replace them. Ideally, NG would only have a single instruction in it,
/// but that may only be possible for store-immediate.
@@ -417,7 +416,6 @@ bool HexagonStoreWidening::createWideSto
Shift += NBits;
}
-
MachineInstr *FirstSt = OG.front();
DebugLoc DL = OG.back()->getDebugLoc();
const MachineMemOperand &OldM = getStoreTarget(FirstSt);
@@ -469,7 +467,6 @@ bool HexagonStoreWidening::createWideSto
return true;
}
-
// Replace instructions from the old group OG with instructions from the
// new group NG. Conceptually, remove all instructions in OG, and then
// insert all instructions in NG, starting at where the first instruction
@@ -534,7 +531,6 @@ bool HexagonStoreWidening::replaceStores
return true;
}
-
// Break up the group into smaller groups, each of which can be replaced by
// a single wide store. Widen each such smaller group and replace the old
// instructions with the widened ones.
@@ -564,7 +560,6 @@ bool HexagonStoreWidening::processStoreG
return Changed;
}
-
// Process a single basic block: create the store groups, and replace them
// with the widened stores, if possible. Processing of each basic block
// is independent from processing of any other basic block. This transfor-
@@ -590,7 +585,6 @@ bool HexagonStoreWidening::processBasicB
return Changed;
}
-
bool HexagonStoreWidening::runOnMachineFunction(MachineFunction &MFn) {
if (skipFunction(*MFn.getFunction()))
return false;
@@ -610,8 +604,6 @@ bool HexagonStoreWidening::runOnMachineF
return Changed;
}
-
FunctionPass *llvm::createHexagonStoreWidening() {
return new HexagonStoreWidening();
}
-
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVectorPrint.cpp Fri Dec 16 19:09:05 2016
@@ -15,8 +15,24 @@
#define DEBUG_TYPE "hexagon-vector-print"
-#include "HexagonTargetMachine.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/InlineAsm.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include <string>
+#include <vector>
using namespace llvm;
@@ -25,40 +41,43 @@ static cl::opt<bool> TraceHexVectorStore
cl::desc("Enables tracing of vector stores"));
namespace llvm {
+
FunctionPass *createHexagonVectorPrint();
void initializeHexagonVectorPrintPass(PassRegistry&);
-}
+} // end namespace llvm
namespace {
class HexagonVectorPrint : public MachineFunctionPass {
- const HexagonSubtarget *QST;
- const HexagonInstrInfo *QII;
- const HexagonRegisterInfo *QRI;
-
- public:
- static char ID;
- HexagonVectorPrint() : MachineFunctionPass(ID),
- QST(0), QII(0), QRI(0) {
- initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
- }
+ const HexagonSubtarget *QST;
+ const HexagonInstrInfo *QII;
+ const HexagonRegisterInfo *QRI;
- StringRef getPassName() const override {
- return "Hexagon VectorPrint pass";
- }
- bool runOnMachineFunction(MachineFunction &Fn) override;
+public:
+ static char ID;
+
+ HexagonVectorPrint()
+ : MachineFunctionPass(ID), QST(nullptr), QII(nullptr), QRI(nullptr) {
+ initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
+ }
+
+ StringRef getPassName() const override { return "Hexagon VectorPrint pass"; }
+
+ bool runOnMachineFunction(MachineFunction &Fn) override;
};
char HexagonVectorPrint::ID = 0;
+} // end anonymous namespace
+
static bool isVecReg(unsigned Reg) {
return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
|| (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
|| (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
}
-std::string getStringReg(unsigned R) {
+static std::string getStringReg(unsigned R) {
if (R >= Hexagon::V0 && R <= Hexagon::V31) {
static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27",
"28", "29", "2a", "2b", "2c", "2d", "2e", "2f",
@@ -138,7 +157,7 @@ bool HexagonVectorPrint::runOnMachineFun
}
}
- Changed = VecPrintList.size() > 0;
+ Changed = !VecPrintList.empty();
if (!Changed)
return Changed;
@@ -179,7 +198,6 @@ bool HexagonVectorPrint::runOnMachineFun
return Changed;
}
-}
//===----------------------------------------------------------------------===//
// Public Constructor Functions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp Fri Dec 16 19:09:05 2016
@@ -13,20 +13,27 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "hexagonmcelfstreamer"
-#include "Hexagon.h"
-#include "HexagonMCELFStreamer.h"
-#include "MCTargetDesc/HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonMCELFStreamer.h"
+#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCShuffler.h"
-#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCObjectStreamer.h"
+#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCSymbolELF.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/ELF.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
+#include <cassert>
+#include <cstdint>
using namespace llvm;
@@ -148,8 +155,10 @@ void HexagonMCELFStreamer::HexagonMCEmit
}
namespace llvm {
+
MCStreamer *createHexagonELFStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_pwrite_stream &OS, MCCodeEmitter *CE) {
return new HexagonMCELFStreamer(Context, MAB, OS, CE);
}
-}
+
+} // end namespace llvm
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h Fri Dec 16 19:09:05 2016
@@ -7,14 +7,14 @@
//
//===----------------------------------------------------------------------===//
-#ifndef HEXAGONMCELFSTREAMER_H
-#define HEXAGONMCELFSTREAMER_H
+#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCELFSTREAMER_H
+#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCELFSTREAMER_H
-#include "MCTargetDesc/HexagonMCCodeEmitter.h"
-#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "llvm/MC/MCELFStreamer.h"
-#include "HexagonTargetStreamer.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include <cstdint>
+#include <memory>
namespace llvm {
@@ -27,8 +27,7 @@ public:
: MCELFStreamer(Context, TAB, OS, Emitter),
MCII(createHexagonMCInstrInfo()) {}
- virtual void EmitInstruction(const MCInst &Inst,
- const MCSubtargetInfo &STI) override;
+ void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
void EmitSymbol(const MCInst &Inst);
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment,
@@ -40,6 +39,6 @@ public:
MCStreamer *createHexagonELFStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_pwrite_stream &OS, MCCodeEmitter *CE);
-} // namespace llvm
+} // end namespace llvm
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCELFSTREAMER_H
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Fri Dec 16 19:09:05 2016
@@ -11,22 +11,27 @@
//
//===----------------------------------------------------------------------===//
-#include "HexagonMCTargetDesc.h"
-#include "Hexagon.h"
-#include "HexagonMCAsmInfo.h"
-#include "HexagonMCELFStreamer.h"
+#include "HexagonTargetStreamer.h"
#include "MCTargetDesc/HexagonInstPrinter.h"
+#include "MCTargetDesc/HexagonMCAsmInfo.h"
+#include "MCTargetDesc/HexagonMCELFStreamer.h"
+#include "MCTargetDesc/HexagonMCTargetDesc.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCObjectStreamer.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/TargetRegistry.h"
+#include <cassert>
+#include <cstdint>
+#include <new>
+#include <string>
using namespace llvm;
@@ -59,7 +64,6 @@ static cl::opt<bool> HexagonV55ArchVaria
static cl::opt<bool> HexagonV60ArchVariant("mv60", cl::Hidden, cl::init(false),
cl::desc("Build for Hexagon V60"));
-
static StringRef DefaultArch = "hexagonv60";
static StringRef HexagonGetArchVariant() {
@@ -108,12 +112,14 @@ createHexagonMCSubtargetInfo(const Tripl
}
namespace {
+
class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
public:
HexagonTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &, bool,
MCInstPrinter &)
: HexagonTargetStreamer(S) {}
+
void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
const MCInst &Inst, const MCSubtargetInfo &STI) override {
assert(HexagonMCInstrInfo::isBundle(Inst));
@@ -145,14 +151,9 @@ public:
OS << "\t}" << PacketBundle.second;
}
};
-}
-namespace {
class HexagonTargetELFStreamer : public HexagonTargetStreamer {
public:
- MCELFStreamer &getStreamer() {
- return static_cast<MCELFStreamer &>(Streamer);
- }
HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
: HexagonTargetStreamer(S) {
auto Bits = STI.getFeatureBits();
@@ -167,6 +168,11 @@ public:
Flags = ELF::EF_HEXAGON_MACH_V4;
getStreamer().getAssembler().setELFHeaderEFlags(Flags);
}
+
+ MCELFStreamer &getStreamer() {
+ return static_cast<MCELFStreamer &>(Streamer);
+ }
+
void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment,
unsigned AccessSize) override {
@@ -175,6 +181,7 @@ public:
HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
AccessSize);
}
+
void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment,
unsigned AccessSize) override {
@@ -184,7 +191,8 @@ public:
Symbol, Size, ByteAlignment, AccessSize);
}
};
-}
+
+} // end anonymous namespace
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) {
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=290024&r1=290023&r2=290024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Fri Dec 16 19:09:05 2016
@@ -14,11 +14,11 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
-#include <cstdint>
-
#include "llvm/Support/CommandLine.h"
+#include <cstdint>
namespace llvm {
+
struct InstrItinerary;
struct InstrStage;
class MCAsmBackend;
@@ -55,10 +55,12 @@ MCObjectWriter *createHexagonELFObjectWr
uint8_t OSABI, StringRef CPU);
namespace Hexagon_MC {
+
StringRef selectHexagonCPU(const Triple &TT, StringRef CPU);
-}
-} // End llvm namespace
+} // end namespace Hexagon_MC
+
+} // end namespace llvm
// Define symbolic names for Hexagon registers. This defines a mapping from
// register name to register number.
@@ -74,4 +76,4 @@ namespace Hexagon_MC {
#define GET_SUBTARGETINFO_ENUM
#include "HexagonGenSubtargetInfo.inc"
-#endif
+#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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