[PATCH] D22398: MIRParser: Allow register class specification on operand

[Matthias Braun via Phabricator via llvm-commits]

MatzeB marked 3 inline comments as done.
MatzeB added inline comments.


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Comment at: test/CodeGen/MIR/X86/register-operand-class.mir:12
+# CHECK:   - { id: 2, class: gr32 }
+# CHECK:   - { id: 3, class: gr16 }
+name: f
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qcolombet wrote:
> We shouldn’t need to emit that part anymore, right?
> Probably a follow-up patch, though.
yep, that is for a followup and needs some policy decisions like what to do with virtual registers that aren't used anywhere.


Repository:
  rL LLVM

https://reviews.llvm.org/D22398