[llvm] r289974 - Implement LaneBitmask::any(), use it to replace !none(), NFCI
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 16 11:11:57 PST 2016
Author: kparzysz
Date: Fri Dec 16 13:11:56 2016
New Revision: 289974
URL: http://llvm.org/viewvc/llvm-project?rev=289974&view=rev
Log:
Implement LaneBitmask::any(), use it to replace !none(), NFCI
Modified:
llvm/trunk/include/llvm/CodeGen/RegisterPressure.h
llvm/trunk/include/llvm/MC/LaneBitmask.h
llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
llvm/trunk/lib/CodeGen/LiveInterval.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/LivePhysRegs.cpp
llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/RegisterPressure.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/trunk/lib/CodeGen/SplitKit.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
llvm/trunk/lib/Target/Hexagon/RDFGraph.h
llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/RegisterPressure.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterPressure.h?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterPressure.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterPressure.h Fri Dec 16 13:11:56 2016
@@ -315,7 +315,7 @@ public:
void appendTo(ContainerT &To) const {
for (const IndexMaskPair &P : Regs) {
unsigned Reg = getRegFromSparseIndex(P.Index);
- if (!P.LaneMask.none())
+ if (P.LaneMask.any())
To.push_back(RegisterMaskPair(Reg, P.LaneMask));
}
}
Modified: llvm/trunk/include/llvm/MC/LaneBitmask.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/LaneBitmask.h?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/LaneBitmask.h (original)
+++ llvm/trunk/include/llvm/MC/LaneBitmask.h Fri Dec 16 13:11:56 2016
@@ -48,6 +48,7 @@ namespace llvm {
constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; }
constexpr bool none() const { return Mask == 0; }
+ constexpr bool any() const { return Mask != 0; }
constexpr bool all() const { return ~Mask == 0; }
constexpr LaneBitmask operator~() const {
Modified: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp (original)
+++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp Fri Dec 16 13:11:56 2016
@@ -482,7 +482,7 @@ bool DetectDeadLanes::isUndefInput(const
const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
- if (!UsedLanes.none())
+ if (UsedLanes.any())
return false;
unsigned MOReg = MO.getReg();
Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Fri Dec 16 13:11:56 2016
@@ -876,7 +876,7 @@ void LiveInterval::computeSubRangeUndefs
const SlotIndexes &Indexes) const {
assert(TargetRegisterInfo::isVirtualRegister(reg));
LaneBitmask VRegMask = MRI.getMaxLaneMaskForVReg(reg);
- assert(!(VRegMask & LaneMask).none());
+ assert((VRegMask & LaneMask).any());
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
for (const MachineOperand &MO : MRI.def_operands(reg)) {
if (!MO.isUndef())
@@ -885,7 +885,7 @@ void LiveInterval::computeSubRangeUndefs
assert(SubReg != 0 && "Undef should only be set on subreg defs");
LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg);
LaneBitmask UndefMask = VRegMask & ~DefMask;
- if (!(UndefMask & LaneMask).none()) {
+ if ((UndefMask & LaneMask).any()) {
const MachineInstr &MI = *MO.getParent();
bool EarlyClobber = MO.isEarlyClobber();
SlotIndex Pos = Indexes.getInstructionIndex(MI).getRegSlot(EarlyClobber);
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Dec 16 13:11:56 2016
@@ -740,7 +740,7 @@ void LiveIntervals::addKillFlags(const V
if (MO.isUse()) {
// Reading any undefined lanes?
LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
- if (!(UseMask & ~DefinedLanesMask).none())
+ if ((UseMask & ~DefinedLanesMask).any())
goto CancelKill;
} else if (MO.getSubReg() == 0) {
// Writing to the full register?
@@ -980,7 +980,7 @@ private:
dbgs() << " ";
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
dbgs() << PrintReg(Reg);
- if (!LaneMask.none())
+ if (LaneMask.any())
dbgs() << " L" << PrintLaneMask(LaneMask);
} else {
dbgs() << PrintRegUnit(Reg, &TRI);
@@ -1314,7 +1314,7 @@ private:
if (MO.isUndef())
continue;
unsigned SubReg = MO.getSubReg();
- if (SubReg != 0 && !LaneMask.none()
+ if (SubReg != 0 && LaneMask.any()
&& (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
continue;
Modified: llvm/trunk/lib/CodeGen/LivePhysRegs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LivePhysRegs.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LivePhysRegs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LivePhysRegs.cpp Fri Dec 16 13:11:56 2016
@@ -144,13 +144,13 @@ bool LivePhysRegs::available(const Machi
void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
for (const auto &LI : MBB.liveins()) {
MCSubRegIndexIterator S(LI.PhysReg, TRI);
- if (LI.LaneMask.all() || (!LI.LaneMask.none() && !S.isValid())) {
+ if (LI.LaneMask.all() || (LI.LaneMask.any() && !S.isValid())) {
addReg(LI.PhysReg);
continue;
}
for (; S.isValid(); ++S) {
unsigned SI = S.getSubRegIndex();
- if (!(LI.LaneMask & TRI->getSubRegIndexLaneMask(SI)).none())
+ if ((LI.LaneMask & TRI->getSubRegIndexLaneMask(SI)).any())
addReg(S.getSubReg());
}
}
Modified: llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp Fri Dec 16 13:11:56 2016
@@ -84,7 +84,7 @@ void LiveRangeCalc::calculate(LiveInterv
LiveInterval::SubRange *CommonRange;
// A Mask for subregs covered by the subrange but not the current def.
LaneBitmask RM = S.LaneMask & ~Mask;
- if (!RM.none()) {
+ if (RM.any()) {
// Split the subrange S into two parts: one covered by the current
// def (CommonRange), and the one not affected by it (updated S).
S.LaneMask = RM;
@@ -98,7 +98,7 @@ void LiveRangeCalc::calculate(LiveInterv
Mask &= ~Common;
}
// Create a new SubRange for subregs we did not cover yet.
- if (!Mask.none()) {
+ if (Mask.any()) {
LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask);
if (MO.isDef())
createDeadDef(*Indexes, *Alloc, *NewRange, MO);
Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Fri Dec 16 13:11:56 2016
@@ -236,7 +236,7 @@ bool LiveRangeEdit::useIsKill(const Live
unsigned SubReg = MO.getSubReg();
LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
for (const LiveInterval::SubRange &S : LI.subranges()) {
- if (!(S.LaneMask & LaneMask).none() && S.Query(Idx).isKill())
+ if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
return true;
}
return false;
Modified: llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp Fri Dec 16 13:11:56 2016
@@ -79,7 +79,7 @@ static bool foreachUnit(const TargetRegi
unsigned Unit = (*Units).first;
LaneBitmask Mask = (*Units).second;
for (LiveInterval::SubRange &S : VRegInterval.subranges()) {
- if (!(S.LaneMask & Mask).none()) {
+ if ((S.LaneMask & Mask).any()) {
if (Func(Unit, S))
return true;
break;
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Fri Dec 16 13:11:56 2016
@@ -346,7 +346,7 @@ void MachineBasicBlock::removeLiveIn(MCP
bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
livein_iterator I = find_if(
LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
- return I != livein_end() && !(I->LaneMask & LaneMask).none();
+ return I != livein_end() && (I->LaneMask & LaneMask).any();
}
void MachineBasicBlock::sortUniqueLiveIns() {
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Fri Dec 16 13:11:56 2016
@@ -1040,7 +1040,7 @@ void ScheduleDAGMILive::updatePressureDi
// this fact anymore => decrement pressure.
// If the register has just become dead then other uses make it come
// back to life => increment pressure.
- bool Decrement = !P.LaneMask.none();
+ bool Decrement = P.LaneMask.any();
for (const VReg2SUnit &V2SU
: make_range(VRegUses.find(Reg), VRegUses.end())) {
@@ -1059,7 +1059,7 @@ void ScheduleDAGMILive::updatePressureDi
);
}
} else {
- assert(!P.LaneMask.none());
+ assert(P.LaneMask.any());
DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
// This may be called before CurrentBottom has been initialized. However,
// BotRPTracker must have a valid position. We want the value live into the
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Dec 16 13:11:56 2016
@@ -482,7 +482,7 @@ void MachineVerifier::report_context(con
LaneBitmask LaneMask) const {
report_context_liverange(LR);
report_context_vreg_regunit(VRegUnit);
- if (!LaneMask.none())
+ if (LaneMask.any())
report_context_lanemask(LaneMask);
}
@@ -1172,7 +1172,7 @@ void MachineVerifier::checkLivenessAtUse
report("Live range continues after kill flag", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
- if (!LaneMask.none())
+ if (LaneMask.any())
report_context_lanemask(LaneMask);
report_context(UseIdx);
}
@@ -1187,7 +1187,7 @@ void MachineVerifier::checkLivenessAtDef
report("Inconsistent valno->def", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
- if (!LaneMask.none())
+ if (LaneMask.any())
report_context_lanemask(LaneMask);
report_context(*VNI);
report_context(DefIdx);
@@ -1196,7 +1196,7 @@ void MachineVerifier::checkLivenessAtDef
report("No live segment at def", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
- if (!LaneMask.none())
+ if (LaneMask.any())
report_context_lanemask(LaneMask);
report_context(DefIdx);
}
@@ -1226,7 +1226,7 @@ void MachineVerifier::checkLivenessAtDef
report("Live range continues after dead def flag", MO, MONum);
report_context_liverange(LR);
report_context_vreg_regunit(VRegOrUnit);
- if (!LaneMask.none())
+ if (LaneMask.any())
report_context_lanemask(LaneMask);
}
}
@@ -1689,7 +1689,7 @@ void MachineVerifier::verifyLiveRangeVal
!TRI->hasRegUnit(MOI->getReg(), Reg))
continue;
}
- if (!LaneMask.none() &&
+ if (LaneMask.any() &&
(TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
continue;
hasDef = true;
@@ -1835,7 +1835,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (MOI->isDead())
hasDeadDef = true;
}
- if (!LaneMask.none() && (LaneMask & SLM).none())
+ if (LaneMask.any() && (LaneMask & SLM).none())
continue;
if (MOI->readsReg())
hasRead = true;
@@ -1854,7 +1854,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (!hasRead) {
// When tracking subregister liveness, the main range must start new
// values on partial register writes, even if there is no read.
- if (!MRI->shouldTrackSubRegLiveness(Reg) || !LaneMask.none() ||
+ if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
!hasSubRegDef) {
report("Instruction ending live segment doesn't read the register",
MI);
@@ -1941,11 +1941,11 @@ void MachineVerifier::verifyLiveInterval
LaneBitmask Mask;
LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
for (const LiveInterval::SubRange &SR : LI.subranges()) {
- if (!(Mask & SR.LaneMask).none()) {
+ if ((Mask & SR.LaneMask).any()) {
report("Lane masks of sub ranges overlap in live interval", MF);
report_context(LI);
}
- if (!(SR.LaneMask & ~MaxMask).none()) {
+ if ((SR.LaneMask & ~MaxMask).any()) {
report("Subrange lanemask is invalid", MF);
report_context(LI);
}
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Fri Dec 16 13:11:56 2016
@@ -822,7 +822,7 @@ bool RegisterCoalescer::removeCopyByComm
<< " into " << PrintLaneMask(Common) << '\n');
LaneBitmask BRest = BMask & ~AMask;
LiveInterval::SubRange *CommonRange;
- if (!BRest.none()) {
+ if (BRest.any()) {
SB.LaneMask = BRest;
DEBUG(dbgs() << "\t\tReduce Lane to " << PrintLaneMask(BRest)
<< '\n');
@@ -841,7 +841,7 @@ bool RegisterCoalescer::removeCopyByComm
addSegmentsWithValNo(*CommonRange, BSubValNo, SA, ASubValNo);
AMask &= ~BMask;
}
- if (!AMask.none()) {
+ if (AMask.any()) {
DEBUG(dbgs() << "\t\tNew Lane " << PrintLaneMask(AMask) << '\n');
LiveRange *NewRange = IntB.createSubRange(Allocator, AMask);
VNInfo *BSubValNo = NewRange->getNextValue(CopyIdx, Allocator);
@@ -1061,7 +1061,7 @@ bool RegisterCoalescer::reMaterializeTri
SR.createDeadDef(DefIndex, Alloc);
MaxMask &= ~SR.LaneMask;
}
- if (!MaxMask.none()) {
+ if (MaxMask.any()) {
LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask);
SR->createDeadDef(DefIndex, Alloc);
}
@@ -1516,7 +1516,7 @@ bool RegisterCoalescer::joinCopy(Machine
updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
// Shrink subregister ranges if necessary.
- if (!ShrinkMask.none()) {
+ if (ShrinkMask.any()) {
LiveInterval &LI = LIS->getInterval(CP.getDstReg());
for (LiveInterval::SubRange &S : LI.subranges()) {
if ((S.LaneMask & ShrinkMask).none())
@@ -1821,7 +1821,7 @@ class JoinVals {
RedefVNI(nullptr), OtherVNI(nullptr), ErasableImplicitDef(false),
Pruned(false), PrunedComputed(false) {}
- bool isAnalyzed() const { return !WriteLanes.none(); }
+ bool isAnalyzed() const { return WriteLanes.any(); }
};
/// One entry per value number in LI.
@@ -2107,7 +2107,7 @@ JoinVals::analyzeValue(unsigned ValNo, J
// predecessor, the PHI itself can't introduce any conflicts.
if (VNI->isPHIDef())
return CR_Merge;
- if (!(V.ValidLanes & OtherV.ValidLanes).none())
+ if ((V.ValidLanes & OtherV.ValidLanes).any())
// Overlapping lanes can't be resolved.
return CR_Impossible;
else
@@ -2261,7 +2261,7 @@ void JoinVals::computeAssignment(unsigne
Val &OtherV = Other.Vals[V.OtherVNI->id];
// We cannot erase an IMPLICIT_DEF if we don't have valid values for all
// its lanes.
- if (!(OtherV.WriteLanes & ~V.ValidLanes).none() && TrackSubRegLiveness)
+ if ((OtherV.WriteLanes & ~V.ValidLanes).any() && TrackSubRegLiveness)
OtherV.ErasableImplicitDef = false;
OtherV.Pruned = true;
LLVM_FALLTHROUGH;
@@ -2322,7 +2322,7 @@ taintExtent(unsigned ValNo, LaneBitmask
TaintedLanes &= ~OV.WriteLanes;
if (!OV.RedefVNI)
break;
- } while (!TaintedLanes.none());
+ } while (TaintedLanes.any());
return true;
}
@@ -2336,7 +2336,7 @@ bool JoinVals::usesLanes(const MachineIn
if (!MO.readsReg())
continue;
unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
- if (!(Lanes & TRI->getSubRegIndexLaneMask(S)).none())
+ if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
return true;
}
return false;
@@ -2732,7 +2732,7 @@ void RegisterCoalescer::mergeSubRangeInt
// they have to split into their own subrange.
LaneBitmask LRest = RMask & ~LaneMask;
LiveInterval::SubRange *CommonRange;
- if (!LRest.none()) {
+ if (LRest.any()) {
R.LaneMask = LRest;
DEBUG(dbgs() << "\t\tReduce Lane to " << PrintLaneMask(LRest) << '\n');
// Duplicate SubRange for newly merged common stuff.
@@ -2747,7 +2747,7 @@ void RegisterCoalescer::mergeSubRangeInt
LaneMask &= ~RMask;
}
- if (!LaneMask.none()) {
+ if (LaneMask.any()) {
DEBUG(dbgs() << "\t\tNew Lane " << PrintLaneMask(LaneMask) << '\n');
LI.createSubRangeFrom(Allocator, LaneMask, ToMerge);
}
@@ -2787,7 +2787,7 @@ bool RegisterCoalescer::joinVirtRegs(Coa
LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
: TRI->getSubRegIndexLaneMask(DstIdx);
// LHS must support subregs or we wouldn't be in this codepath.
- assert(!Mask.none());
+ assert(Mask.any());
LHS.createSubRangeFrom(Allocator, Mask, LHS);
} else if (DstIdx != 0) {
// Transform LHS lanemasks to new register class if necessary.
Modified: llvm/trunk/lib/CodeGen/RegisterPressure.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterPressure.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterPressure.cpp Fri Dec 16 13:11:56 2016
@@ -27,7 +27,7 @@ static void increaseSetPressure(std::vec
const MachineRegisterInfo &MRI, unsigned Reg,
LaneBitmask PrevMask, LaneBitmask NewMask) {
assert((PrevMask & ~NewMask).none() && "Must not remove bits");
- if (!PrevMask.none() || NewMask.none())
+ if (PrevMask.any() || NewMask.none())
return;
PSetIterator PSetI = MRI.getPressureSets(Reg);
@@ -41,7 +41,7 @@ static void decreaseSetPressure(std::vec
const MachineRegisterInfo &MRI, unsigned Reg,
LaneBitmask PrevMask, LaneBitmask NewMask) {
//assert((NewMask & !PrevMask) == 0 && "Must not add bits");
- if (!NewMask.none() || PrevMask.none())
+ if (NewMask.any() || PrevMask.none())
return;
PSetIterator PSetI = MRI.getPressureSets(Reg);
@@ -112,7 +112,7 @@ void PressureDiff::dump(const TargetRegi
void RegPressureTracker::increaseRegPressure(unsigned RegUnit,
LaneBitmask PreviousMask,
LaneBitmask NewMask) {
- if (!PreviousMask.none() || NewMask.none())
+ if (PreviousMask.any() || NewMask.none())
return;
PSetIterator PSetI = MRI->getPressureSets(RegUnit);
@@ -339,7 +339,7 @@ static LaneBitmask getRegLanes(ArrayRef<
static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
RegisterMaskPair Pair) {
unsigned RegUnit = Pair.RegUnit;
- assert(!Pair.LaneMask.none());
+ assert(Pair.LaneMask.any());
auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
return Other.RegUnit == RegUnit;
});
@@ -365,7 +365,7 @@ static void setRegZero(SmallVectorImpl<R
static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
RegisterMaskPair Pair) {
unsigned RegUnit = Pair.RegUnit;
- assert(!Pair.LaneMask.none());
+ assert(Pair.LaneMask.any());
auto I = find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
return Other.RegUnit == RegUnit;
});
@@ -671,7 +671,7 @@ void RegPressureTracker::addLiveRegs(Arr
void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
SmallVectorImpl<RegisterMaskPair> &LiveInOrOut) {
- assert(!Pair.LaneMask.none());
+ assert(Pair.LaneMask.any());
unsigned RegUnit = Pair.RegUnit;
auto I = find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
@@ -735,7 +735,7 @@ void RegPressureTracker::recede(const Re
LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
- if (!LiveOut.none()) {
+ if (LiveOut.any()) {
discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
// Retroactively model effects on pressure of the live out lanes.
increaseSetPressure(CurrSetPressure, *MRI, Reg, LaneBitmask::getNone(),
@@ -760,7 +760,7 @@ void RegPressureTracker::recede(const Re
// Generate liveness for uses.
for (const RegisterMaskPair &Use : RegOpers.Uses) {
unsigned Reg = Use.RegUnit;
- assert(!Use.LaneMask.none());
+ assert(Use.LaneMask.any());
LaneBitmask PreviousMask = LiveRegs.insert(Use);
LaneBitmask NewMask = PreviousMask | Use.LaneMask;
if (NewMask == PreviousMask)
@@ -789,7 +789,7 @@ void RegPressureTracker::recede(const Re
// Discover live outs if this may be the first occurance of this register.
if (RequireIntervals) {
LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
- if (!LiveOut.none())
+ if (LiveOut.any())
discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
}
}
@@ -866,7 +866,7 @@ void RegPressureTracker::advance(const R
unsigned Reg = Use.RegUnit;
LaneBitmask LiveMask = LiveRegs.contains(Reg);
LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
- if (!LiveIn.none()) {
+ if (LiveIn.any()) {
discoverLiveIn(RegisterMaskPair(Reg, LiveIn));
increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
@@ -874,7 +874,7 @@ void RegPressureTracker::advance(const R
// Kill liveness at last uses.
if (RequireIntervals) {
LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
- if (!LastUseMask.none()) {
+ if (LastUseMask.any()) {
LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
}
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Fri Dec 16 13:11:56 2016
@@ -34,7 +34,7 @@ using namespace llvm;
void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
LaneBitmask UnitMask = (*RUI).second;
- if (UnitMask.none() || !(LaneMask & UnitMask).none())
+ if (UnitMask.none() || (LaneMask & UnitMask).any())
RegUnitsAvailable.reset((*RUI).first);
}
}
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Fri Dec 16 13:11:56 2016
@@ -449,7 +449,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(S
continue;
}
- if (!(LaneMask & DefLaneMask).none()) {
+ if ((LaneMask & DefLaneMask).any()) {
SUnit *UseSU = I->SU;
MachineInstr *Use = UseSU->getInstr();
SDep Dep(SU, SDep::Data, Reg);
@@ -461,7 +461,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(S
LaneMask &= ~KillLaneMask;
// If we found a Def for all lanes of this use, remove it from the list.
- if (!LaneMask.none()) {
+ if (LaneMask.any()) {
I->LaneMask = LaneMask;
++I;
} else
@@ -507,11 +507,11 @@ void ScheduleDAGInstrs::addVRegDefDeps(S
LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
V2SU.SU = SU;
V2SU.LaneMask = OverlapMask;
- if (!NonOverlapMask.none())
+ if (NonOverlapMask.any())
CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
}
// If there was no CurrentVRegDefs entry for some lanes yet, create one.
- if (!LaneMask.none())
+ if (LaneMask.any())
CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
}
Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Fri Dec 16 13:11:56 2016
@@ -425,7 +425,7 @@ void SplitEditor::addDeadDef(LiveInterva
}
}
for (LiveInterval::SubRange &S : LI.subranges())
- if (!(S.LaneMask & LM).none())
+ if ((S.LaneMask & LM).any())
S.createDeadDef(Def, LIS.getVNInfoAllocator());
}
}
Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Fri Dec 16 13:11:56 2016
@@ -342,7 +342,7 @@ bool VirtRegRewriter::readsUndefSubreg(c
LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
// See if any of the relevant subregister liveranges is defined at this point.
for (const LiveInterval::SubRange &SR : LI.subranges()) {
- if (!(SR.LaneMask & UseMask).none() && SR.liveAt(BaseIndex))
+ if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
return false;
}
return true;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp Fri Dec 16 13:11:56 2016
@@ -240,7 +240,7 @@ HexagonBlockRanges::RegisterSet HexagonB
}
for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) {
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if (!(M & I.LaneMask).none())
+ if ((M & I.LaneMask).any())
Tmp.insert({S.getSubReg(), 0});
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Fri Dec 16 13:11:56 2016
@@ -369,7 +369,7 @@ void HexagonExpandCondsets::updateDeadsI
if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
return false;
LaneBitmask SLM = getLaneMask(DR, DSR);
- return !(SLM & LM).none();
+ return (SLM & LM).any();
};
// The splitting step will create pairs of predicated definitions without
Modified: llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFGraph.cpp Fri Dec 16 13:11:56 2016
@@ -662,7 +662,7 @@ bool RegisterAggr::hasAliasOf(RegisterRe
RegisterRef NR = normalize(RR);
auto F = Masks.find(NR.Reg);
if (F != Masks.end()) {
- if (!(F->second & NR.Mask).none())
+ if ((F->second & NR.Mask).any())
return true;
}
if (CheckUnits) {
@@ -1089,7 +1089,7 @@ RegisterRef DataFlowGraph::normalizeRef(
RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
if (AR.Reg == BR.Reg) {
LaneBitmask M = AR.Mask & BR.Mask;
- return !M.none() ? RegisterRef(AR.Reg, M) : RegisterRef();
+ return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
}
#ifndef NDEBUG
RegisterRef NAR = normalizeRef(AR);
@@ -1221,7 +1221,7 @@ bool DataFlowGraph::alias(RegisterRef RA
// while the lane mask of r2 in d1 may be 0b0001.
LaneBitmask LA = PA.second & RA.Mask;
LaneBitmask LB = PB.second & RB.Mask;
- if (!LA.none() && !LB.none()) {
+ if (LA.any() && LB.any()) {
unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI);
// If register units were guaranteed to only have 1 bit in any lane
// mask, the code below would not be necessary. This is because LA
@@ -1232,7 +1232,7 @@ bool DataFlowGraph::alias(RegisterRef RA
const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root);
LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA);
LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB);
- if (!(MaskA & MaskB & RC.LaneMask).none())
+ if ((MaskA & MaskB & RC.LaneMask).any())
return true;
}
Modified: llvm/trunk/lib/Target/Hexagon/RDFGraph.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFGraph.h?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFGraph.h (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFGraph.h Fri Dec 16 13:11:56 2016
@@ -405,7 +405,7 @@ namespace rdf {
RegisterRef() : RegisterRef(0) {}
explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
: Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
- operator bool() const { return Reg != 0 && !Mask.none(); }
+ operator bool() const { return Reg != 0 && Mask.any(); }
bool operator== (const RegisterRef &RR) const {
return Reg == RR.Reg && Mask == RR.Mask;
}
@@ -471,11 +471,11 @@ namespace rdf {
return K == 0 ? LaneBitmask::getAll() : get(K);
}
uint32_t getIndexForLaneMask(LaneBitmask LM) {
- assert(!LM.none());
+ assert(LM.any());
return LM.all() ? 0 : insert(LM);
}
uint32_t getIndexForLaneMask(LaneBitmask LM) const {
- assert(!LM.none());
+ assert(LM.any());
return LM.all() ? 0 : find(LM);
}
PackedRegisterRef pack(RegisterRef RR) {
Modified: llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp Fri Dec 16 13:11:56 2016
@@ -710,7 +710,7 @@ void Liveness::computeLiveIns() {
}
do {
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if (!(M & P.second).none())
+ if ((M & P.second).any())
LV.push_back(RegisterRef(S.getSubReg()));
++S;
} while (S.isValid());
@@ -759,7 +759,7 @@ void Liveness::resetKills(MachineBasicBl
}
do {
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if (!(M & I.LaneMask).none())
+ if ((M & I.LaneMask).any())
LV.set(S.getSubReg());
++S;
} while (S.isValid());
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Fri Dec 16 13:11:56 2016
@@ -104,7 +104,7 @@ void CodeGenSubRegIndex::updateComponent
LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
// Already computed?
- if (!LaneMask.none())
+ if (LaneMask.any())
return LaneMask;
// Recursion guard, shouldn't be required.
@@ -114,7 +114,7 @@ LaneBitmask CodeGenSubRegIndex::computeL
LaneBitmask M;
for (const auto &C : Composed)
M |= C.second->computeLaneMask();
- assert(!M.none() && "Missing lane mask, sub-register cycle?");
+ assert(M.any() && "Missing lane mask, sub-register cycle?");
LaneMask = M;
return LaneMask;
}
@@ -1267,7 +1267,7 @@ void CodeGenRegBank::computeSubRegLaneMa
SrcMask = LaneBitmask::getNone();
}
}
- if (!SrcMask.none()) {
+ if (SrcMask.any()) {
MaskRolPair MaskRol = { SrcMask, RotateLeft };
LaneTransforms.push_back(MaskRol);
}
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=289974&r1=289973&r2=289974&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Dec 16 13:11:56 2016
@@ -776,7 +776,7 @@ RegisterInfoEmitter::emitComposeSubRegIn
" --IdxA; assert(IdxA < " << SubRegIndices.size()
<< " && \"Subregister index out of bounds\");\n"
" LaneBitmask Result;\n"
- " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; !Ops->Mask.none(); ++Ops) {\n"
+ " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n"
" LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n"
" if (unsigned S = Ops->RotateLeft)\n"
" Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n"
@@ -793,7 +793,7 @@ RegisterInfoEmitter::emitComposeSubRegIn
" --IdxA; assert(IdxA < " << SubRegIndices.size()
<< " && \"Subregister index out of bounds\");\n"
" LaneBitmask Result;\n"
- " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; !Ops->Mask.none(); ++Ops) {\n"
+ " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n"
" LaneBitmask::Type M = LaneMask.getAsInteger();\n"
" if (unsigned S = Ops->RotateLeft)\n"
" Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n"
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