[PATCH] D27845: [SelectionDAG] Enable target specific vector scalarization of calls and returns

[Simon Dardis via Phabricator via llvm-commits]

sdardis created this revision.
sdardis added reviewers: zoran.jovanovic, jaydeep.
sdardis added a subscriber: llvm-commits.
sdardis set the repository for this revision to rL LLVM.
Herald added a reviewer: vkalintiris.

By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.

The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle raw LLVM-IR with vector types in calls and returns.

Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.

By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular form scalarization
of vectors.

Previously, the MIPS backend relied on clang to scalarize types such as "call
(<4 x float> %a) into "call (i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".

This patch enables the MIPS backend to take either form for vector types.


Repository:
  rL LLVM

https://reviews.llvm.org/D27845

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  lib/CodeGen/SelectionDAG/StatepointLowering.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Target/Mips/MipsCCState.cpp
  lib/Target/Mips/MipsCCState.h
  lib/Target/Mips/MipsCallingConv.td
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/Mips/MipsISelLowering.h
  lib/Target/Mips/MipsRegisterInfo.cpp
  test/CodeGen/Mips/cconv/vector.ll
  test/CodeGen/Mips/ctlz-v.ll
  test/CodeGen/Mips/cttz-v.ll
  test/CodeGen/Mips/return-vector.ll

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