[llvm] r289863 - [LV] Enable vectorization of loops with conditional stores by default

Fri Dec 16 03:42:28 PST 2016

I've reverted this in r289934 as it caused the loop vectorizer to crash in
the Python runtime on PPC.

You should be able to reproduce by running 'opt -loop-vectorize' over:
https://reviews.llvm.org/P7949

On Thu, Dec 15, 2016 at 12:21 PM Matthew Simpson via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: mssimpso
> Date: Thu Dec 15 14:11:05 2016
> New Revision: 289863
>
> URL: http://llvm.org/viewvc/llvm-project?rev=289863&view=rev
> Log:
> [LV] Enable vectorization of loops with conditional stores by default
>
> This patch sets the default value of the "-enable-cond-stores-vec" command
> line
> option to "true".
>
> Differential Revision: https://reviews.llvm.org/D27814
>
> Modified:
>     llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp
>     llvm/trunk/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
>     llvm/trunk/test/Transforms/LoopVectorize/conditional-assignment.ll
>     llvm/trunk/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
>     llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll
>
> llvm/trunk/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
>
> Modified: llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=289863&r1=289862&r2=289863&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp (original)
> +++ llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp Thu Dec 15
> 14:11:05 2016
> @@ -191,7 +191,7 @@ static cl::opt<bool> EnableIndVarRegiste
>      cl::desc("Count the induction variable only once when interleaving"));
>
>  static cl::opt<bool> EnableCondStoresVectorization(
> -    "enable-cond-stores-vec", cl::init(false), cl::Hidden,
> +    "enable-cond-stores-vec", cl::init(true), cl::Hidden,
>      cl::desc("Enable if predication of stores during vectorization."));
>
>  static cl::opt<unsigned> MaxNestedScalarReductionIC(
>
> Modified:
> llvm/trunk/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/predication_costs.ll?rev=289863&r1=289862&r2=289863&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
> (original)
> +++ llvm/trunk/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
> Thu Dec 15 14:11:05 2016
> @@ -1,5 +1,5 @@
>  ; REQUIRES: asserts
> -; RUN: opt < %s -force-vector-width=2 -enable-cond-stores-vec
> -loop-vectorize -debug-only=loop-vectorize -disable-output 2>&1 | FileCheck
> %s
> +; RUN: opt < %s -force-vector-width=2 -loop-vectorize
> -debug-only=loop-vectorize -disable-output 2>&1 | FileCheck %s
>
>  target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
>  target triple = "aarch64--linux-gnu"
>
> Modified:
> llvm/trunk/test/Transforms/LoopVectorize/conditional-assignment.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/conditional-assignment.ll?rev=289863&r1=289862&r2=289863&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/Transforms/LoopVectorize/conditional-assignment.ll
> (original)
> +++ llvm/trunk/test/Transforms/LoopVectorize/conditional-assignment.ll Thu
> Dec 15 14:11:05 2016
> @@ -1,5 +1,5 @@
> -; RUN: opt < %s -loop-vectorize -S -pass-remarks-missed='loop-vectorize'
> -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s
> -; RUN: opt < %s -passes=loop-vectorize -S
> -pass-remarks-missed='loop-vectorize'
> -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s
> +; RUN: opt < %s -enable-cond-stores-vec=false -loop-vectorize -S
> -pass-remarks-missed='loop-vectorize'
> -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s
> +; RUN: opt < %s -enable-cond-stores-vec=false -passes=loop-vectorize -S
> -pass-remarks-missed='loop-vectorize'
> -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s
>
>  ; CHECK: remark: source.c:2:8: loop not vectorized: store that is
> conditionally executed prevents vectorization
>
>
> Modified:
> llvm/trunk/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll?rev=289863&r1=289862&r2=289863&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
> (original)
> +++ llvm/trunk/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
> Thu Dec 15 14:11:05 2016
> @@ -1,6 +1,6 @@
>  ; REQUIRES: asserts
>  ; RUN: opt < %s -loop-vectorize -force-vector-width=4
> -force-vector-interleave=1 -instcombine -debug-only=loop-vectorize
> -disable-output -print-after=instcombine 2>&1 | FileCheck %s
> -; RUN: opt < %s -loop-vectorize -force-vector-width=4
> -force-vector-interleave=1 -enable-interleaved-mem-accesses
> -enable-cond-stores-vec -instcombine -debug-only=loop-vectorize
> -disable-output -print-after=instcombine 2>&1 | FileCheck %s
> --check-prefix=INTER
> +; RUN: opt < %s -loop-vectorize -force-vector-width=4
> -force-vector-interleave=1 -enable-interleaved-mem-accesses -instcombine
> -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 |
> FileCheck %s --check-prefix=INTER
>
>  target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
>
>
> Modified: llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll?rev=289863&r1=289862&r2=289863&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll (original)
> +++ llvm/trunk/test/Transforms/LoopVectorize/if-pred-stores.ll Thu Dec 15
> 14:11:05 2016
> @@ -1,6 +1,6 @@
>  ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1
> -force-vector-interleave=2 -loop-vectorize -verify-loop-info -simplifycfg <
> %s | FileCheck %s --check-prefix=UNROLL
>  ; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1
> -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s |
> FileCheck %s --check-prefix=UNROLL-NOSIMPLIFY
> -; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2
> -force-vector-interleave=1 -loop-vectorize -enable-cond-stores-vec
> -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
> +; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2
> -force-vector-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg <
> %s | FileCheck %s --check-prefix=VEC
>
>  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
>
>
> Modified:
> llvm/trunk/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll?rev=289863&r1=289862&r2=289863&view=diff
>
> ==============================================================================
> ---
> llvm/trunk/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
> (original)
> +++
> llvm/trunk/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
> Thu Dec 15 14:11:05 2016
> @@ -1,4 +1,4 @@
> -; RUN: opt -S -loop-vectorize -instcombine -force-vector-width=2
> -force-vector-interleave=1 -enable-interleaved-mem-accesses
> -vectorize-num-stores-pred=1 -enable-cond-stores-vec < %s | FileCheck %s
> +; RUN: opt -S -loop-vectorize -instcombine -force-vector-width=2
> -force-vector-interleave=1 -enable-interleaved-mem-accesses < %s |
> FileCheck %s
>
>  target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
>  %pair = type { i64, i64 }
>
>
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