[PATCH] D27695: Add Instruction number to LSR cost model (PR23384)

[Wei Mi via Phabricator via llvm-commits]

wmi added a comment.

Thanks for working on it. We also noticed the same problem and wanted it to be fixed.

> 1. Add instructions number generated by a solution to LSR cost
> 2. Move LSR cost comparison to target part

2. seems a good idea for me, because for arch with post load/store increments addinc cost are not as significant as the cost on arches like x86 without the support.

It may be separated as a NFC patch?

> 3. Add new cross use generation for ICmpZero that ends with zero

Can it be split into a separate patch?



================
Comment at: lib/Transforms/Scalar/LoopStrengthReduce.cpp:917
+  }
 
+  bool isLower(Cost &Other, const TargetTransformInfo &TTI);
----------------
Better to use member initializer list? Cost() : C({0, 0, ... ,0}) {}


================
Comment at: lib/Transforms/Scalar/LoopStrengthReduce.cpp:1208
+  }
+
   // Determine how many (unfolded) adds we'll need inside the loop.
----------------
C.NumRegs only calculate the regs used in induction var expr so it is not a good estimation for register number used in the loop. It can be much less than the real register number used.

We can have a utility like that in vectorization to get a better register number estimation used in the loop, but that can be in a further enhancement.  Before we have such a utility in place, I would rather conservatively think every loop has high register pressure,  and always add C.NumRegs  into C.Insns.  I think it avoids the case that LSR significantly increase register pressure just to reduce one addinc. 


Repository:
  rL LLVM

https://reviews.llvm.org/D27695