[llvm] r289898 - [AArch64] Add FeatureSlowMisaligned128Store to Exynos M1 and M2

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Thu Dec 15 18:18:00 2016
New Revision: 289898

URL: http://llvm.org/viewvc/llvm-project?rev=289898&view=rev
Log:
[AArch64] Add FeatureSlowMisaligned128Store to Exynos M1 and M2

This feature now gates such stores after r289845.  Thus the Exynos
processors now need this feature.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=289898&r1=289897&r2=289898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Dec 15 18:18:00 2016
@@ -230,6 +230,7 @@ def ProcExynosM1 : SubtargetFeature<"exy
                                      FeatureNEON,
                                      FeaturePerfMon,
                                      FeaturePostRAScheduler,
+                                     FeatureSlowMisaligned128Store,
                                      FeatureUseRSqrt,
                                      FeatureZCZeroing]>;
 
@@ -243,6 +244,7 @@ def ProcExynosM2 : SubtargetFeature<"exy
                                      FeatureNEON,
                                      FeaturePerfMon,
                                      FeaturePostRAScheduler,
+                                     FeatureSlowMisaligned128Store,
                                      FeatureZCZeroing]>;
 
 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",