[llvm] r289636 - [X86][InstCombine] Teach SimplifyDemandedVectorElts to handle masked scalar add/sub/mul/div/max/min intrinsics better.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 22:06:58 PST 2016
Author: ctopper
Date: Wed Dec 14 00:06:58 2016
New Revision: 289636
URL: http://llvm.org/viewvc/llvm-project?rev=289636&view=rev
Log:
[X86][InstCombine] Teach SimplifyDemandedVectorElts to handle masked scalar add/sub/mul/div/max/min intrinsics better.
Now we can remove these intrinsics if element 0 isn't used. Also fix undef element tracking.
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/trunk/test/Transforms/InstCombine/x86-avx512.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=289636&r1=289635&r2=289636&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed Dec 14 00:06:58 2016
@@ -1754,6 +1754,7 @@ Instruction *InstCombiner::visitCallInst
break;
}
+ // X86 scalar intrinsics simplified with SimplifyDemandedVectorElts.
case Intrinsic::x86_avx512_mask_add_ss_round:
case Intrinsic::x86_avx512_mask_div_ss_round:
case Intrinsic::x86_avx512_mask_mul_ss_round:
@@ -1765,26 +1766,7 @@ Instruction *InstCombiner::visitCallInst
case Intrinsic::x86_avx512_mask_mul_sd_round:
case Intrinsic::x86_avx512_mask_sub_sd_round:
case Intrinsic::x86_avx512_mask_max_sd_round:
- case Intrinsic::x86_avx512_mask_min_sd_round: {
- // These intrinsics only demand the lowest element of the second and third
- // input vector.
- bool MadeChange = false;
- Value *Arg1 = II->getArgOperand(1);
- Value *Arg2 = II->getArgOperand(2);
- unsigned VWidth = Arg1->getType()->getVectorNumElements();
- if (Value *V = SimplifyDemandedVectorEltsLow(Arg1, VWidth, 1)) {
- II->setArgOperand(1, V);
- MadeChange = true;
- }
- if (Value *V = SimplifyDemandedVectorEltsLow(Arg2, VWidth, 1)) {
- II->setArgOperand(2, V);
- MadeChange = true;
- }
- if (MadeChange)
- return II;
- break;
- }
-
+ case Intrinsic::x86_avx512_mask_min_sd_round:
case Intrinsic::x86_fma_vfmadd_ss:
case Intrinsic::x86_fma_vfmsub_ss:
case Intrinsic::x86_fma_vfnmadd_ss:
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=289636&r1=289635&r2=289636&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Wed Dec 14 00:06:58 2016
@@ -1352,6 +1352,18 @@ Value *InstCombiner::SimplifyDemandedVec
// Three input scalar-as-vector operations that work column-wise. The high
// elements come from operand 0 and the low element is a function of all
// three inputs.
+ case Intrinsic::x86_avx512_mask_add_ss_round:
+ case Intrinsic::x86_avx512_mask_div_ss_round:
+ case Intrinsic::x86_avx512_mask_mul_ss_round:
+ case Intrinsic::x86_avx512_mask_sub_ss_round:
+ case Intrinsic::x86_avx512_mask_max_ss_round:
+ case Intrinsic::x86_avx512_mask_min_ss_round:
+ case Intrinsic::x86_avx512_mask_add_sd_round:
+ case Intrinsic::x86_avx512_mask_div_sd_round:
+ case Intrinsic::x86_avx512_mask_mul_sd_round:
+ case Intrinsic::x86_avx512_mask_sub_sd_round:
+ case Intrinsic::x86_avx512_mask_max_sd_round:
+ case Intrinsic::x86_avx512_mask_min_sd_round:
case Intrinsic::x86_fma_vfmadd_ss:
case Intrinsic::x86_fma_vfmsub_ss:
case Intrinsic::x86_fma_vfnmadd_ss:
Modified: llvm/trunk/test/Transforms/InstCombine/x86-avx512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/x86-avx512.ll?rev=289636&r1=289635&r2=289636&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/x86-avx512.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/x86-avx512.ll Wed Dec 14 00:06:58 2016
@@ -28,6 +28,23 @@ define <4 x float> @test_add_ss_mask(<4
ret <4 x float> %4
}
+define float @test_add_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_add_ss_1(
+; CHECK-NEXT: ret float 1.000000e+00
+;
+ %1 = insertelement <4 x float> undef, float %a, i32 0
+ %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+ %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+ %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+ %5 = insertelement <4 x float> undef, float %b, i32 0
+ %6 = insertelement <4 x float> %1, float 4.000000e+00, i32 1
+ %7 = insertelement <4 x float> %2, float 5.000000e+00, i32 2
+ %8 = insertelement <4 x float> %3, float 6.000000e+00, i32 3
+ %9 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 4)
+ %10 = extractelement <4 x float> %9, i32 1
+ ret float %10
+}
+
declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
@@ -50,6 +67,19 @@ define <2 x double> @test_add_sd_mask(<2
ret <2 x double> %2
}
+define double @test_add_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_add_sd_1(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %1 = insertelement <2 x double> undef, double %a, i32 0
+ %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+ %3 = insertelement <2 x double> undef, double %b, i32 0
+ %4 = insertelement <2 x double> %1, double 2.000000e+00, i32 1
+ %5 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 4)
+ %6 = extractelement <2 x double> %5, i32 1
+ ret double %6
+}
+
declare <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
@@ -76,6 +106,23 @@ define <4 x float> @test_sub_ss_mask(<4
ret <4 x float> %4
}
+define float @test_sub_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_sub_ss_1(
+; CHECK-NEXT: ret float 1.000000e+00
+;
+ %1 = insertelement <4 x float> undef, float %a, i32 0
+ %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+ %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+ %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+ %5 = insertelement <4 x float> undef, float %b, i32 0
+ %6 = insertelement <4 x float> %1, float 4.000000e+00, i32 1
+ %7 = insertelement <4 x float> %2, float 5.000000e+00, i32 2
+ %8 = insertelement <4 x float> %3, float 6.000000e+00, i32 3
+ %9 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 4)
+ %10 = extractelement <4 x float> %9, i32 1
+ ret float %10
+}
+
declare <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
@@ -98,6 +145,19 @@ define <2 x double> @test_sub_sd_mask(<2
ret <2 x double> %2
}
+define double @test_sub_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_sub_sd_1(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %1 = insertelement <2 x double> undef, double %a, i32 0
+ %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+ %3 = insertelement <2 x double> undef, double %b, i32 0
+ %4 = insertelement <2 x double> %1, double 2.000000e+00, i32 1
+ %5 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 4)
+ %6 = extractelement <2 x double> %5, i32 1
+ ret double %6
+}
+
declare <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
@@ -124,6 +184,23 @@ define <4 x float> @test_mul_ss_mask(<4
ret <4 x float> %4
}
+define float @test_mul_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_mul_ss_1(
+; CHECK-NEXT: ret float 1.000000e+00
+;
+ %1 = insertelement <4 x float> undef, float %a, i32 0
+ %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+ %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+ %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+ %5 = insertelement <4 x float> undef, float %b, i32 0
+ %6 = insertelement <4 x float> %1, float 4.000000e+00, i32 1
+ %7 = insertelement <4 x float> %2, float 5.000000e+00, i32 2
+ %8 = insertelement <4 x float> %3, float 6.000000e+00, i32 3
+ %9 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 4)
+ %10 = extractelement <4 x float> %9, i32 1
+ ret float %10
+}
+
declare <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
@@ -146,6 +223,19 @@ define <2 x double> @test_mul_sd_mask(<2
ret <2 x double> %2
}
+define double @test_mul_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_mul_sd_1(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %1 = insertelement <2 x double> undef, double %a, i32 0
+ %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+ %3 = insertelement <2 x double> undef, double %b, i32 0
+ %4 = insertelement <2 x double> %1, double 2.000000e+00, i32 1
+ %5 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 4)
+ %6 = extractelement <2 x double> %5, i32 1
+ ret double %6
+}
+
declare <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
@@ -172,6 +262,23 @@ define <4 x float> @test_div_ss_mask(<4
ret <4 x float> %4
}
+define float @test_div_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_div_ss_1(
+; CHECK-NEXT: ret float 1.000000e+00
+;
+ %1 = insertelement <4 x float> undef, float %a, i32 0
+ %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+ %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+ %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+ %5 = insertelement <4 x float> undef, float %b, i32 0
+ %6 = insertelement <4 x float> %1, float 4.000000e+00, i32 1
+ %7 = insertelement <4 x float> %2, float 5.000000e+00, i32 2
+ %8 = insertelement <4 x float> %3, float 6.000000e+00, i32 3
+ %9 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 4)
+ %10 = extractelement <4 x float> %9, i32 1
+ ret float %10
+}
+
declare <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
@@ -194,6 +301,19 @@ define <2 x double> @test_div_sd_mask(<2
ret <2 x double> %2
}
+define double @test_div_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_div_sd_1(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %1 = insertelement <2 x double> undef, double %a, i32 0
+ %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+ %3 = insertelement <2 x double> undef, double %b, i32 0
+ %4 = insertelement <2 x double> %1, double 2.000000e+00, i32 1
+ %5 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 4)
+ %6 = extractelement <2 x double> %5, i32 1
+ ret double %6
+}
+
declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
@@ -220,6 +340,23 @@ define <4 x float> @test_max_ss_mask(<4
ret <4 x float> %4
}
+define float @test_max_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_max_ss_1(
+; CHECK-NEXT: ret float 1.000000e+00
+;
+ %1 = insertelement <4 x float> undef, float %a, i32 0
+ %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+ %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+ %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+ %5 = insertelement <4 x float> undef, float %b, i32 0
+ %6 = insertelement <4 x float> %1, float 4.000000e+00, i32 1
+ %7 = insertelement <4 x float> %2, float 5.000000e+00, i32 2
+ %8 = insertelement <4 x float> %3, float 6.000000e+00, i32 3
+ %9 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 4)
+ %10 = extractelement <4 x float> %9, i32 1
+ ret float %10
+}
+
declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
@@ -242,6 +379,19 @@ define <2 x double> @test_max_sd_mask(<2
ret <2 x double> %2
}
+define double @test_max_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_max_sd_1(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %1 = insertelement <2 x double> undef, double %a, i32 0
+ %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+ %3 = insertelement <2 x double> undef, double %b, i32 0
+ %4 = insertelement <2 x double> %1, double 2.000000e+00, i32 1
+ %5 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 4)
+ %6 = extractelement <2 x double> %5, i32 1
+ ret double %6
+}
+
declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
@@ -268,6 +418,23 @@ define <4 x float> @test_min_ss_mask(<4
ret <4 x float> %4
}
+define float @test_min_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_min_ss_1(
+; CHECK-NEXT: ret float 1.000000e+00
+;
+ %1 = insertelement <4 x float> undef, float %a, i32 0
+ %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+ %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+ %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+ %5 = insertelement <4 x float> undef, float %b, i32 0
+ %6 = insertelement <4 x float> %1, float 4.000000e+00, i32 1
+ %7 = insertelement <4 x float> %2, float 5.000000e+00, i32 2
+ %8 = insertelement <4 x float> %3, float 6.000000e+00, i32 3
+ %9 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 4)
+ %10 = extractelement <4 x float> %9, i32 1
+ ret float %10
+}
+
declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
@@ -290,6 +457,19 @@ define <2 x double> @test_min_sd_mask(<2
ret <2 x double> %2
}
+define double @test_min_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_min_sd_1(
+; CHECK-NEXT: ret double 1.000000e+00
+;
+ %1 = insertelement <2 x double> undef, double %a, i32 0
+ %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+ %3 = insertelement <2 x double> undef, double %b, i32 0
+ %4 = insertelement <2 x double> %1, double 2.000000e+00, i32 1
+ %5 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 4)
+ %6 = extractelement <2 x double> %5, i32 1
+ ret double %6
+}
+
declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)
define i8 @test_cmp_ss(<4 x float> %a, <4 x float> %b, i8 %mask) {
More information about the llvm-commits
mailing list