[PATCH] D27677: [AArch64] Guard Misaligned 128-bit store penalty by subtarget feature

[Matthew Simpson via Phabricator via llvm-commits]

mssimpso added a comment.

In https://reviews.llvm.org/D27677#620254, @evandro wrote:

> I actually wonder if, for uniformity's sake, `FeatureAvoidQuadLdStPairs` should be renamed `FeatureSlow256LoadStore`.  Thoughts?


We can certainly discuss renaming that feature, but I think we should probably do so in a separate review/thread.

> BTW, is FeatureSlowMisaligned128Store really meant for v2i64 only and for no other 128-bit vector type?

It doesn't look like the feature is limited to v2i64. The fact that the TTI function explicitly checks for an integer type seems wrong to me. But I think Matthias is probably right in that this heuristic was originally intended for Cyclone. It looks fairly clear to me that the heuristic should be guarded by FeatureSlowMisaligned128Store. This will preserve the existing functionality for Cyclone, but will change the other subtargets. Would you have any concerns for Exynos were this the case?


https://reviews.llvm.org/D27677