[PATCH] D27624: [ARM] Split 128-bit vectors in BUILD_VECTOR lowering

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

Hi Eli,

This change looks good to me. I just have a small comment inline.

cheers,
--renato



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Comment at: lib/Target/ARM/ARMISelLowering.cpp:6232
+      Upper = LowerBUILD_VECTOR(Upper, DAG, ST);
+    if (Lower && Upper)
+      return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);
----------------
I'm assuming `LowerBUILD_VECTOR` can return `SDNode()` if there's no need for it, thus the concat only happening if both were lowered.

Is this is your strategy around "we might discover a better way to lower it"?

How can we avoid cases where it doesn't?


Repository:
  rL LLVM

https://reviews.llvm.org/D27624