[PATCH] D27692: [x86] use a single shufps when it can save instructions

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, delena, zvi, DavidKreitzer, zansari, mkuper, craig.topper.
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This is a tiny patch with a big pile of test changes.

My motivating case looks like this:

- vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
- vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
- vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]

+    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]

And this happens several times in the diffs. I think the instruction count and size reduction overcomes any potential domain-crossing penalty due to using an FP op in a sequence of int ops, but let me know if you see problem cases.

I think these are all improvements except one test in vector-shuffle-combining.ll where we miss an opportunity to use a shift to generate zero elements and one test in combine-sra.ll where I'm not sure what is happening yet.


https://reviews.llvm.org/D27692

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/SwizzleShuff.ll
  test/CodeGen/X86/avx-trunc.ll
  test/CodeGen/X86/combine-or.ll
  test/CodeGen/X86/combine-shl.ll
  test/CodeGen/X86/combine-sra.ll
  test/CodeGen/X86/combine-srem.ll
  test/CodeGen/X86/combine-srl.ll
  test/CodeGen/X86/combine-urem.ll
  test/CodeGen/X86/compress_expand.ll
  test/CodeGen/X86/i64-to-float.ll
  test/CodeGen/X86/masked_gather_scatter.ll
  test/CodeGen/X86/masked_memop.ll
  test/CodeGen/X86/oddshuffles.ll
  test/CodeGen/X86/palignr.ll
  test/CodeGen/X86/pmul.ll
  test/CodeGen/X86/reduce-trunc-shl.ll
  test/CodeGen/X86/sse-fsignum.ll
  test/CodeGen/X86/vec_fp_to_int.ll
  test/CodeGen/X86/vector-compare-results.ll
  test/CodeGen/X86/vector-shuffle-128-v4.ll
  test/CodeGen/X86/vector-shuffle-combining.ll
  test/CodeGen/X86/vector-trunc-math.ll
  test/CodeGen/X86/vector-trunc.ll
  test/CodeGen/X86/vsplit-and.ll

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