[PATCH] D27684: [X86][SSE] Fix domains for VZEXT_LOAD type instructions

[Zia Ansari via Phabricator via llvm-commits]

zansari added a comment.

I'm working on getting some confirmation on the latest ones, but most current Core architectures suffer a 1-clk penalty switching between fp and int domains. This doesn't include the Atom line, which can do it for free.

The 1 clk isn't insignificant if you're latency bound and you do a lot of switching on the critical path. I'm not familiar with the code that decides to switch, but can it take architectures and maybe code size into consideration (i.e. favor smaller encoding with Os/Oz)?


Repository:
  rL LLVM

https://reviews.llvm.org/D27684