[PATCH] D26367: Fix DAGCombiner match

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D26367#599175, @evstupac wrote:

>   ldrb r12, [lr, r12]!
>   ldrb lr, [lr, #1]
>
>
> Instead of 1 ldrh.


The question here is: Is LLVM emitting one LDRH today, or is it already emitting two LDRBs?

If the former, than this is a regression. If the latter, than you can safely ignore ARM.

The AArch64 side looks good, but I'd also like to know if we were emitting two byte-loads before.

However, even on the ARM side, this looks more like and issue on the ARM code-gen than on the DAG combiner, so it should be fine to push this through and fix the ARM code-gen later.

But we need to know what's the behaviour today, so that we can correctly fill the bug we open on ARM, to mention if it is a regression or not.

cheers,
--renato


Repository:
  rL LLVM

https://reviews.llvm.org/D26367