[PATCH] D27657: [X86][SSE] Lower suitably sign-extended mul vXi64 using PMULDQ

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: test/CodeGen/X86/vector-compare-results.ll:1884
+; AVX512-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
+; AVX512-NEXT:    vmovdqa %xmm4, %xmm2
 ; AVX512-NEXT:    retq
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This change seems unrelated to the multiply changes. Was it caused by the computeSignBits changes handling for extract subvector?


Repository:
  rL LLVM

https://reviews.llvm.org/D27657