[llvm] r289232 - [SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 9 09:53:12 PST 2016
Author: rksimon
Date: Fri Dec 9 11:53:11 2016
New Revision: 289232
URL: http://llvm.org/viewvc/llvm-project?rev=289232&view=rev
Log:
[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED)
Reapplied with fix for PR31323 - X86 SSE2 vXi16 multiplies for illegal types were creating CONCAT_VECTORS nodes with vector inputs that might not total the number of elements in the result type.
Added:
llvm/trunk/test/CodeGen/X86/pr31323.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=289232&r1=289231&r2=289232&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Dec 9 11:53:11 2016
@@ -2631,6 +2631,42 @@ void SelectionDAG::computeKnownBits(SDVa
}
break;
}
+ case ISD::INSERT_VECTOR_ELT: {
+ SDValue InVec = Op.getOperand(0);
+ SDValue InVal = Op.getOperand(1);
+ SDValue EltNo = Op.getOperand(2);
+
+ ConstantSDNode *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
+ if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
+ // If we know the element index, split the demand between the
+ // source vector and the inserted element.
+ KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
+ unsigned EltIdx = CEltNo->getZExtValue();
+
+ // If we demand the inserted element then add its common known bits.
+ if (DemandedElts[EltIdx]) {
+ computeKnownBits(InVal, KnownZero2, KnownOne2, Depth + 1);
+ KnownOne &= KnownOne2.zextOrTrunc(KnownOne.getBitWidth());
+ KnownZero &= KnownZero2.zextOrTrunc(KnownZero.getBitWidth());;
+ }
+
+ // If we demand the source vector then add its common known bits, ensuring
+ // that we don't demand the inserted element.
+ APInt VectorElts = DemandedElts & ~(APInt::getOneBitSet(NumElts, EltIdx));
+ if (!!VectorElts) {
+ computeKnownBits(InVec, KnownZero2, KnownOne2, VectorElts, Depth + 1);
+ KnownOne &= KnownOne2;
+ KnownZero &= KnownZero2;
+ }
+ } else {
+ // Unknown element index, so ignore DemandedElts and demand them all.
+ computeKnownBits(InVec, KnownZero, KnownOne, Depth + 1);
+ computeKnownBits(InVal, KnownZero2, KnownOne2, Depth + 1);
+ KnownOne &= KnownOne2.zextOrTrunc(KnownOne.getBitWidth());
+ KnownZero &= KnownZero2.zextOrTrunc(KnownZero.getBitWidth());;
+ }
+ break;
+ }
case ISD::BSWAP: {
computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
Depth + 1);
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=289232&r1=289231&r2=289232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 9 11:53:11 2016
@@ -29387,7 +29387,12 @@ static SDValue reduceVMULWidth(SDNode *N
// <4 x i16> undef).
//
// Legalize the operands of mul.
- SmallVector<SDValue, 16> Ops(RegSize / ReducedVT.getSizeInBits(),
+ // FIXME: We may be able to handle non-concatenated vectors by insertion.
+ unsigned ReducedSizeInBits = ReducedVT.getSizeInBits();
+ if ((RegSize % ReducedSizeInBits) != 0)
+ return SDValue();
+
+ SmallVector<SDValue, 16> Ops(RegSize / ReducedSizeInBits,
DAG.getUNDEF(ReducedVT));
Ops[0] = NewN0;
NewN0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, OpsVT, Ops);
Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=289232&r1=289231&r2=289232&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Fri Dec 9 11:53:11 2016
@@ -58,11 +58,7 @@ define <4 x float> @knownbits_insert_uit
; X32-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0
; X32-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-NEXT: vpsrld $16, %xmm0, %xmm0
-; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0
+; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_insert_uitofp:
@@ -72,11 +68,7 @@ define <4 x float> @knownbits_insert_uit
; X64-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0
; X64-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X64-NEXT: vpsrld $16, %xmm0, %xmm0
-; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X64-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0
+; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq
%1 = zext i16 %a1 to i32
%2 = zext i16 %a2 to i32
Added: llvm/trunk/test/CodeGen/X86/pr31323.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr31323.ll?rev=289232&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr31323.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr31323.ll Fri Dec 9 11:53:11 2016
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
+
+; Reduced test case.
+
+define i32 @pr31323(i32) {
+; X32-LABEL: pr31323:
+; X32: # BB#0: # %entry
+; X32-NEXT: xorl %eax, %eax
+; X32-NEXT: retl
+;
+; X64-LABEL: pr31323:
+; X64: # BB#0: # %entry
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: retq
+entry:
+ %1 = and i32 %0, 31
+ %2 = insertelement <3 x i32> undef, i32 %1, i32 0
+ %3 = shufflevector <3 x i32> %2, <3 x i32> undef, <3 x i32> zeroinitializer
+ %4 = insertelement <3 x i8> undef, i8 0, i32 2
+ %5 = zext <3 x i8> %4 to <3 x i32>
+ %6 = mul nsw <3 x i32> %3, %5
+ %7 = ashr <3 x i32> %6, <i32 10, i32 10, i32 10>
+ %8 = extractelement <3 x i32> %7, i32 0
+ ret i32 %8
+}
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