[llvm] r289230 - AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 9 09:49:12 PST 2016
Author: arsenm
Date: Fri Dec 9 11:49:11 2016
New Revision: 289230
URL: http://llvm.org/viewvc/llvm-project?rev=289230&view=rev
Log:
AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
Fixes assembler regressions.
Modified:
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/trunk/test/MC/AMDGPU/smem.s
llvm/trunk/test/MC/AMDGPU/smrd.s
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=289230&r1=289229&r2=289230&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Fri Dec 9 11:49:11 2016
@@ -283,13 +283,13 @@ def TTMP_64 : RegisterClass<"AMDGPU", [v
}
def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
- (add SGPR_64, VCC, FLAT_SCR)> {
+ (add SGPR_64, VCC, FLAT_SCR, TTMP_64, TBA, TMA)> {
let CopyCost = 1;
let AllocationPriority = 2;
}
def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
- (add SReg_64_XEXEC, EXEC, TTMP_64, TBA, TMA)> {
+ (add SReg_64_XEXEC, EXEC)> {
let CopyCost = 1;
let AllocationPriority = 2;
}
Modified: llvm/trunk/test/MC/AMDGPU/smem.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smem.s?rev=289230&r1=289229&r2=289230&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smem.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smem.s Fri Dec 9 11:49:11 2016
@@ -17,6 +17,18 @@ s_memrealtime s[4:5]
// VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
+s_memrealtime tba
+// VI: s_memrealtime tba ; encoding: [0x00,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_memrealtime tma
+// VI: s_memrealtime tma ; encoding: [0x80,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_memrealtime ttmp[0:1]
+// VI: s_memrealtime ttmp[0:1] ; encoding: [0x00,0x1c,0x94,0xc0,0x00,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
// FIXME: Should error about instruction on GPU
s_store_dword s1, s[2:3], 0xfc
// VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
@@ -27,13 +39,29 @@ s_store_dword s1, s[2:3], 0xfc glc
// NOSICI: error: invalid operand for instruction
s_store_dword s1, s[2:3], s4
-// VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
+// VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
s_store_dword s1, s[2:3], s4 glc
// VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
// NOSICI: error: invalid operand for instruction
+s_store_dword tba_lo, s[2:3], s4
+// VI: s_store_dword tba_lo, s[2:3], s4 ; encoding: [0x01,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_store_dword tba_hi, s[2:3], s4
+// VI: s_store_dword tba_hi, s[2:3], s4 ; encoding: [0x41,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_store_dword tma_lo, s[2:3], s4
+// VI: s_store_dword tma_lo, s[2:3], s4 ; encoding: [0x81,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_store_dword tma_hi, s[2:3], s4
+// VI: s_store_dword tma_hi, s[2:3], s4 ; encoding: [0xc1,0x1b,0x40,0xc0,0x04,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
// FIXME: Should error on SI instead of silently ignoring glc
s_load_dword s1, s[2:3], 0xfc glc
// VI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
@@ -45,6 +73,26 @@ s_buffer_store_dword s10, s[92:95], m0
// VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
+s_buffer_store_dword tba_lo, s[92:95], m0
+// VI: s_buffer_store_dword tba_lo, s[92:95], m0 ; encoding: [0x2e,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_buffer_store_dword tba_hi, s[92:95], m0
+// VI: s_buffer_store_dword tba_hi, s[92:95], m0 ; encoding: [0x6e,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_buffer_store_dword tma_lo, s[92:95], m0
+// VI: s_buffer_store_dword tma_lo, s[92:95], m0 ; encoding: [0xae,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_buffer_store_dword tma_hi, s[92:95], m0
+// VI: s_buffer_store_dword tma_hi, s[92:95], m0 ; encoding: [0xee,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_buffer_store_dword ttmp0, s[92:95], m0
+// VI: s_buffer_store_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1c,0x60,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
s_buffer_store_dwordx2 s[10:11], s[92:95], m0
// VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
@@ -53,14 +101,50 @@ s_buffer_store_dwordx4 s[8:11], s[92:95]
// VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
// NOSICI: error: invalid operand for instruction
+s_buffer_store_dwordx2 tba, s[92:95], m0 glc
+// VI: s_buffer_store_dwordx2 tba, s[92:95], m0 glc ; encoding: [0x2e,0x1b,0x65,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: invalid operand for instruction
+
s_buffer_load_dword s10, s[92:95], m0
// VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
+s_buffer_load_dword tba_lo, s[92:95], m0
+// VI: s_buffer_load_dword tba_lo, s[92:95], m0 ; encoding: [0x2e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dword tba_lo, s[92:95], m0 ; encoding: [0x7c,0x5c,0x36,0xc2]
+
+s_buffer_load_dword tba_hi, s[92:95], m0
+// VI: s_buffer_load_dword tba_hi, s[92:95], m0 ; encoding: [0x6e,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dword tba_hi, s[92:95], m0 ; encoding: [0x7c,0xdc,0x36,0xc2]
+
+s_buffer_load_dword tma_lo, s[92:95], m0
+// VI: s_buffer_load_dword tma_lo, s[92:95], m0 ; encoding: [0xae,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dword tma_lo, s[92:95], m0 ; encoding: [0x7c,0x5c,0x37,0xc2]
+
+s_buffer_load_dword tma_hi, s[92:95], m0
+// VI: s_buffer_load_dword tma_hi, s[92:95], m0 ; encoding: [0xee,0x1b,0x20,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dword tma_hi, s[92:95], m0 ; encoding: [0x7c,0xdc,0x37,0xc2]
+
+s_buffer_load_dword ttmp0, s[92:95], m0
+// VI: s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x2e,0x1c,0x20,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dword ttmp0, s[92:95], m0 ; encoding: [0x7c,0x5c,0x38,0xc2]
+
s_buffer_load_dwordx2 s[10:11], s[92:95], m0
// VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
// SICI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0x7c,0x5c,0x45,0xc2]
+s_buffer_load_dwordx2 tba, s[92:95], m0
+// VI: s_buffer_load_dwordx2 tba, s[92:95], m0 ; encoding: [0x2e,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dwordx2 tba, s[92:95], m0 ; encoding: [0x7c,0x5c,0x76,0xc2]
+
+s_buffer_load_dwordx2 tma, s[92:95], m0
+// VI: s_buffer_load_dwordx2 tma, s[92:95], m0 ; encoding: [0xae,0x1b,0x24,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dwordx2 tma, s[92:95], m0 ; encoding: [0x7c,0x5c,0x77,0xc2]
+
+s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0
+// VI: s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x2e,0x1c,0x24,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dwordx2 ttmp[0:1], s[92:95], m0 ; encoding: [0x7c,0x5c,0x78,0xc2]
+
// FIXME: Should error on SI instead of silently ignoring glc
s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
// VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
Modified: llvm/trunk/test/MC/AMDGPU/smrd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd.s?rev=289230&r1=289229&r2=289230&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smrd.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smrd.s Fri Dec 9 11:49:11 2016
@@ -45,11 +45,31 @@ s_load_dword s1, s[2:3], 0xffffffff
s_load_dword s1, s[2:3], 1
// GCN: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0]
-// VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
+// VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
s_load_dword s1, s[2:3], s4
// GCN: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
-// VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
+// VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dword tba_lo, s[2:3], s4
+// GCN: s_load_dword tba_lo, s[2:3], s4 ; encoding: [0x04,0x02,0x36,0xc0]
+// VI: s_load_dword tba_lo, s[2:3], s4 ; encoding: [0x01,0x1b,0x00,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dword tba_hi, s[2:3], s4
+// GCN: s_load_dword tba_hi, s[2:3], s4 ; encoding: [0x04,0x82,0x36,0xc0]
+// VI: s_load_dword tba_hi, s[2:3], s4 ; encoding: [0x41,0x1b,0x00,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dword tma_lo, s[2:3], s4
+// GCN: s_load_dword tma_lo, s[2:3], s4 ; encoding: [0x04,0x02,0x37,0xc0]
+// VI: s_load_dword tma_lo, s[2:3], s4 ; encoding: [0x81,0x1b,0x00,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dword tma_hi, s[2:3], s4
+// GCN: s_load_dword tma_hi, s[2:3], s4 ; encoding: [0x04,0x82,0x37,0xc0]
+// VI: s_load_dword tma_hi, s[2:3], s4 ; encoding: [0xc1,0x1b,0x00,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dword ttmp0, s[2:3], s4
+// GCN: s_load_dword ttmp0, s[2:3], s4 ; encoding: [0x04,0x02,0x38,0xc0]
+// VI: s_load_dword ttmp0, s[2:3], s4 ; encoding: [0x01,0x1c,0x00,0xc0,0x04,0x00,0x00,0x00]
s_load_dwordx2 s[2:3], s[2:3], 1
// GCN: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0]
@@ -59,6 +79,18 @@ s_load_dwordx2 s[2:3], s[2:3], s4
// GCN: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0]
// VI: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x81,0x00,0x04,0xc0,0x04,0x00,0x00,0x00]
+s_load_dwordx2 tba, s[2:3], s4
+// GCN: s_load_dwordx2 tba, s[2:3], s4 ; encoding: [0x04,0x02,0x76,0xc0]
+// VI: s_load_dwordx2 tba, s[2:3], s4 ; encoding: [0x01,0x1b,0x04,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dwordx2 tma, s[2:3], s4
+// GCN: s_load_dwordx2 tma, s[2:3], s4 ; encoding: [0x04,0x02,0x77,0xc0]
+// VI: s_load_dwordx2 tma, s[2:3], s4 ; encoding: [0x81,0x1b,0x04,0xc0,0x04,0x00,0x00,0x00]
+
+s_load_dwordx2 ttmp[2:3], s[2:3], s4
+// GCN: s_load_dwordx2 ttmp[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x79,0xc0]
+// VI: s_load_dwordx2 ttmp[2:3], s[2:3], s4 ; encoding: [0x81,0x1c,0x04,0xc0,0x04,0x00,0x00,0x00]
+
s_load_dwordx4 s[4:7], s[2:3], 1
// GCN: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0]
// VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
@@ -105,7 +137,23 @@ s_buffer_load_dword s1, s[4:7], 1
s_buffer_load_dword s1, s[4:7], s4
// GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2]
-// VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
+// VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dword tba_lo, s[4:7], s4
+// GCN: s_buffer_load_dword tba_lo, s[4:7], s4 ; encoding: [0x04,0x04,0x36,0xc2]
+// VI: s_buffer_load_dword tba_lo, s[4:7], s4 ; encoding: [0x02,0x1b,0x20,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dword tba_hi, s[4:7], s4
+// GCN: s_buffer_load_dword tba_hi, s[4:7], s4 ; encoding: [0x04,0x84,0x36,0xc2]
+// VI: s_buffer_load_dword tba_hi, s[4:7], s4 ; encoding: [0x42,0x1b,0x20,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dword tma_lo, s[4:7], s4
+// GCN: s_buffer_load_dword tma_lo, s[4:7], s4 ; encoding: [0x04,0x04,0x37,0xc2]
+// VI: s_buffer_load_dword tma_lo, s[4:7], s4 ; encoding: [0x82,0x1b,0x20,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dword tma_hi, s[4:7], s4
+// GCN: s_buffer_load_dword tma_hi, s[4:7], s4 ; encoding: [0x04,0x84,0x37,0xc2]
+// VI: s_buffer_load_dword tma_hi, s[4:7], s4 ; encoding: [0xc2,0x1b,0x20,0xc0,0x04,0x00,0x00,0x00]
s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4
// GCN: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]
@@ -119,6 +167,14 @@ s_buffer_load_dwordx2 s[8:9], s[4:7], s4
// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x04,0x04,0x44,0xc2]
// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x02,0x02,0x24,0xc0,0x04,0x00,0x00,0x00]
+s_buffer_load_dwordx2 tba, s[4:7], s4
+// GCN: s_buffer_load_dwordx2 tba, s[4:7], s4 ; encoding: [0x04,0x04,0x76,0xc2]
+// VI: s_buffer_load_dwordx2 tba, s[4:7], s4 ; encoding: [0x02,0x1b,0x24,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 tma, s[4:7], s4
+// GCN: s_buffer_load_dwordx2 tma, s[4:7], s4 ; encoding: [0x04,0x04,0x77,0xc2]
+// VI: s_buffer_load_dwordx2 tma, s[4:7], s4 ; encoding: [0x82,0x1b,0x24,0xc0,0x04,0x00,0x00,0x00]
+
s_buffer_load_dwordx4 s[8:11], s[4:7], 1
// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x01,0x05,0x84,0xc2]
// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2a,0xc0,0x01,0x00,0x00,0x00]
@@ -170,4 +226,12 @@ s_dcache_inv_vol
s_memtime s[4:5]
// GCN: s_memtime s[4:5] ; encoding: [0x00,0x00,0x82,0xc7]
-// VI: s_memtime s[4:5] ; encoding: [0x00,0x01,0x90,0xc0,0x00,0x00,0x00,0x00]
+// VI: s_memtime s[4:5] ; encoding: [0x00,0x01,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime tba
+// GCN: s_memtime tba ; encoding: [0x00,0x00,0xb6,0xc7]
+// VI: s_memtime tba ; encoding: [0x00,0x1b,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime tma
+// GCN: s_memtime tma ; encoding: [0x00,0x00,0xb7,0xc7]
+// VI: s_memtime tma ; encoding: [0x80,0x1b,0x90,0xc0,0x00,0x00,0x00,0x00]
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