[PATCH] D27611: [X86] Remove some intrinsic instructions from hasPartialRegUpdate

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, zvi.
craig.topper added a subscriber: llvm-commits.

These intrinsic instructions are all selected from intrinsics that have well defined behavior for where the upper bits come from. It's not the same place as the lower bits.

As you can see we were suppressing load folding for these instructions in some cases. In none of the cases was the separate load helping avoid a partial dependency on the destination register. So we should just go ahead and allow the load to be folded.

Only foldMemoryOperand was suppressing folding for these. They all have patterns for folding sse_load_f32/f64 that aren't gated with OptForSize, but sse_load_f32/f64 doesn't allow 128-bit vector loads. It only allows scalar_to_vector and vzmovl of scalar loads to match. There's no reason we can't allow a 128-bit vector load to be narrowed so I would like to fix sse_load_f32/f64 to allow that. And if I do that it changes some of these same test cases to fold the load too.


https://reviews.llvm.org/D27611

Files:
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
  test/CodeGen/X86/sse2-intrinsics-x86.ll
  test/CodeGen/X86/sse_partial_update.ll
  test/CodeGen/X86/vec_ss_load_fold.ll

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