[PATCH] D27609: Fix R_AARCH64_MOVW_UABS_G3 relocation

[Yichao Yu via Phabricator via llvm-commits]

yuyichao created this revision.
yuyichao added a reviewer: t.p.northover.
yuyichao added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

The relocation is missing mask so an address that has non-zero bits in 47:43 may overwrite the register number. (Frequently shows up as target register changed to `xzr`....)


https://reviews.llvm.org/D27609

Files:
  lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp


Index: lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
===================================================================
--- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -357,7 +357,7 @@
     // bits affected by the relocation on entry is garbage.
     *TargetPtr &= 0xffe0001fU;
     // Immediate goes in bits 20:5 of MOVZ/MOVK instruction
-    *TargetPtr |= Result >> (48 - 5);
+    *TargetPtr |= ((Result & 0xffff000000000000ULL) >> (48 - 5));
     // Shift must be "lsl #48", in bits 22:21
     assert((*TargetPtr >> 21 & 0x3) == 3 && "invalid shift for relocation");
     break;


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