[llvm] r289031 - [AVR] Add MIR tests for a few pseudo instructions

[Dylan McKay via llvm-commits]

Author: dylanmckay
Date: Thu Dec  8 02:54:41 2016
New Revision: 289031

URL: http://llvm.org/viewvc/llvm-project?rev=289031&view=rev
Log:
[AVR] Add MIR tests for a few pseudo instructions

Added:
    llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir

Added: llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir?rev=289031&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir Thu Dec  8 02:54:41 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit add pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_addwrdrr() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_addwrdrr
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_addwrdrr
+
+    ; CHECK:       %r14 = ADDRdRr %r14, %r20, implicit-def %sreg
+    ; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+
+    %r15r14 = ADDWRdRr %r15r14, %r21r20, implicit-def %sreg
+...

Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir?rev=289031&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir Thu Dec  8 02:54:41 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0  %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_lddwrdptrq() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_lddwrdptrq
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_lddwrdptrq
+
+    ; CHECK:      ldd     r30, Y+10
+    ; CHECK-NEXT: ldd     r31, Y+11
+
+    early-clobber %r31r30 = LDDWRdPtrQ %r29r28, 10
+...

Added: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir?rev=289031&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir (added)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir Thu Dec  8 02:54:41 2016
@@ -0,0 +1,24 @@
+# RUN: llc -O0  %s -o - 2>&1 | FileCheck %s
+
+# This test checks the expansion of the 16-bit 'LDDWRdYQ instruction
+
+--- |
+  target triple = "avr--"
+  define void @test_lddwrdyq() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_lddwrdyq
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: test_lddwrdyq
+
+    ; CHECK:      ldd     r30, Y+1
+    ; CHECK-NEXT: ldd     r31, Y+2
+
+    early-clobber %r31r30 = LDDWRdYQ %r29r28, 1
+...