[llvm] r288980 - GlobalISel: simplify MachineIRBuilder interface.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 7 18:54:41 PST 2016
Hi Tim,
Just double checking.
One concern I had was that I was afraid the iterator could be invalided by some other insertion/deletion, whereas the pointers are not (unless you delete the related object of course). I admit I didn’t checked the MachineBasicBlock implementation back then, so they may have been unnecessary.
Do you concur my worries were ill-founded?
Thanks,
-Quentin
> On Dec 7, 2016, at 1:05 PM, Tim Northover via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: tnorthover
> Date: Wed Dec 7 15:05:38 2016
> New Revision: 288980
>
> URL: http://llvm.org/viewvc/llvm-project?rev=288980&view=rev
> Log:
> GlobalISel: simplify MachineIRBuilder interface.
>
> MachineIRBuilder had weird before/after and beginning/end flags for the insert
> point. Unfortunately the non-default means that instructions will be inserted
> in reverse order which is almost never what anyone wants.
>
> Really, I think we just want (like IRBuilder has) the ability to insert at any
> C++ iterator-style point (i.e. before any instruction or before MBB.end()). So
> this fixes MIRBuilders to behave like IRBuilders in this respect.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
> llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
> llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
> llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
> llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
> llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
>
> Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Wed Dec 7 15:05:38 2016
> @@ -48,8 +48,7 @@ class MachineIRBuilder {
> /// Fields describing the insertion point.
> /// @{
> MachineBasicBlock *MBB;
> - MachineInstr *MI;
> - bool Before;
> + MachineBasicBlock::iterator II;
> /// @}
>
> std::function<void(MachineInstr *)> InsertedInstr;
> @@ -75,22 +74,28 @@ public:
> }
>
> /// Current insertion point for new instructions.
> - MachineBasicBlock::iterator getInsertPt();
> + MachineBasicBlock::iterator getInsertPt() {
> + return II;
> + }
> +
> + /// Set the insertion point before the specified position.
> + /// \pre MBB must be in getMF().
> + /// \pre II must be a valid iterator in MBB.
> + void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II);
> + /// @}
>
> /// Setters for the insertion point.
> /// @{
> /// Set the MachineFunction where to build instructions.
> void setMF(MachineFunction &);
>
> - /// Set the insertion point to the beginning (\p Beginning = true) or end
> - /// (\p Beginning = false) of \p MBB.
> + /// Set the insertion point to the end of \p MBB.
> /// \pre \p MBB must be contained by getMF().
> - void setMBB(MachineBasicBlock &MBB, bool Beginning = false);
> + void setMBB(MachineBasicBlock &MBB);
>
> - /// Set the insertion point to before (\p Before = true) or after
> - /// (\p Before = false) \p MI.
> + /// Set the insertion point to before MI.
> /// \pre MI must be in getMF().
> - void setInstr(MachineInstr &MI, bool Before = true);
> + void setInstr(MachineInstr &MI);
> /// @}
>
> /// Control where instructions we create are recorded (typically for
>
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Wed Dec 7 15:05:38 2016
> @@ -744,13 +744,18 @@ bool IRTranslator::runOnMachineFunction(
>
> assert(PendingPHIs.empty() && "stale PHIs");
>
> - // Setup the arguments.
> - MachineBasicBlock &MBB = getOrCreateBB(F.front());
> - MIRBuilder.setMBB(MBB);
> + // Setup a separate basic-block for the arguments and constants, falling
> + // through to the IR-level Function's entry block.
> + MachineBasicBlock *EntryBB = MF.CreateMachineBasicBlock();
> + MF.push_back(EntryBB);
> + EntryBB->addSuccessor(&getOrCreateBB(F.front()));
> + EntryBuilder.setMBB(*EntryBB);
> +
> + // Lower the actual args into this basic block.
> SmallVector<unsigned, 8> VRegArgs;
> for (const Argument &Arg: F.args())
> VRegArgs.push_back(getOrCreateVReg(Arg));
> - bool Succeeded = CLI->lowerFormalArguments(MIRBuilder, F, VRegArgs);
> + bool Succeeded = CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs);
> if (!Succeeded) {
> if (!TPC->isGlobalISelAbortEnabled()) {
> MIRBuilder.getMF().getProperties().set(
> @@ -761,13 +766,7 @@ bool IRTranslator::runOnMachineFunction(
> report_fatal_error("Unable to lower arguments");
> }
>
> - // Now that we've got the ABI handling code, it's safe to set a location for
> - // any Constants we find in the IR.
> - if (MBB.empty())
> - EntryBuilder.setMBB(MBB, /* Beginning */ true);
> - else
> - EntryBuilder.setInstr(MBB.back(), /* Before */ false);
> -
> + // And translate the function!
> for (const BasicBlock &BB: F) {
> MachineBasicBlock &MBB = getOrCreateBB(BB);
> // Set the insertion point of all the following translations to
>
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Wed Dec 7 15:05:38 2016
> @@ -27,34 +27,29 @@ void MachineIRBuilder::setMF(MachineFunc
> this->MRI = &MF.getRegInfo();
> this->TII = MF.getSubtarget().getInstrInfo();
> this->DL = DebugLoc();
> - this->MI = nullptr;
> + this->II = MachineBasicBlock::iterator();
> this->InsertedInstr = nullptr;
> }
>
> -void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
> +void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
> this->MBB = &MBB;
> - this->MI = nullptr;
> - Before = Beginning;
> + this->II = MBB.end();
> assert(&getMF() == MBB.getParent() &&
> "Basic block is in a different function");
> }
>
> -void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
> +void MachineIRBuilder::setInstr(MachineInstr &MI) {
> assert(MI.getParent() && "Instruction is not part of a basic block");
> setMBB(*MI.getParent());
> - this->MI = &MI;
> - this->Before = Before;
> + this->II = MI.getIterator();
> }
>
> -MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
> - if (MI) {
> - if (Before)
> - return MI;
> - if (!MI->getNextNode())
> - return getMBB().end();
> - return MI->getNextNode();
> - }
> - return Before ? getMBB().begin() : getMBB().end();
> +void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
> + MachineBasicBlock::iterator II) {
> + assert(MBB.getParent() == &getMF() &&
> + "Basic block is in a different function");
> + this->MBB = &MBB;
> + this->II = II;
> }
>
> void MachineIRBuilder::recordInsertions(
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp Wed Dec 7 15:05:38 2016
> @@ -200,12 +200,10 @@ bool AArch64CallLowering::lowerReturn(Ma
> MachineFunction &MF = MIRBuilder.getMF();
> const Function &F = *MF.getFunction();
>
> - MachineInstrBuilder MIB = MIRBuilder.buildInstr(AArch64::RET_ReallyLR);
> - assert(MIB.getInstr() && "Unable to build a return instruction?!");
> -
> + auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
> assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
> + bool Success = true;
> if (VReg) {
> - MIRBuilder.setInstr(*MIB.getInstr(), /* Before */ true);
> const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
> CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
> MachineRegisterInfo &MRI = MF.getRegInfo();
> @@ -221,9 +219,11 @@ bool AArch64CallLowering::lowerReturn(Ma
> });
>
> OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
> - return handleAssignments(MIRBuilder, AssignFn, SplitArgs, Handler);
> + Success = handleAssignments(MIRBuilder, AssignFn, SplitArgs, Handler);
> }
> - return true;
> +
> + MIRBuilder.insertInstr(MIB);
> + return Success;
> }
>
> bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Wed Dec 7 15:05:38 2016
> @@ -7,8 +7,9 @@ target triple = "aarch64--"
>
> ; Tests for add.
> ; CHECK-LABEL: name: addi64
> -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> +; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> @@ -20,6 +21,7 @@ define i64 @addi64(i64 %arg1, i64 %arg2)
> ; CHECK-LABEL: name: muli64
> ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> @@ -51,11 +53,13 @@ define void @allocai64() {
> ; CHECK-LABEL: name: uncondbr
> ; CHECK: body:
> ;
> -; Entry basic block.
> -; CHECK: {{[0-9a-zA-Z._-]+}}:
> +; ABI/constant lowering basic block.
> +; CHECK: {{bb.[0-9]+}}:
> +; IR-level entry basic block
> +; CHECK: {{bb.[0-9]+}}:
> ;
> ; Make sure we have one successor and only one.
> -; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]](0x80000000)
> +; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
> ;
> ; Check that we emit the correct branch.
> ; CHECK: G_BR %[[END]]
> @@ -73,15 +77,18 @@ end:
> ; CHECK-LABEL: name: condbr
> ; CHECK: body:
> ;
> -; Entry basic block.
> -; CHECK: {{[0-9a-zA-Z._-]+}}:
> +; ABI/constant lowering basic block.
> +; CHECK: {{bb.[0-9]+}}:
> +; CHECK: [[ADDR:%.*]](p0) = COPY %x0
> +
> +; IR-level entry basic block
> +; CHECK: {{bb.[0-9]+}}:
> ;
> ; Make sure we have two successors
> -; CHECK-NEXT: successors: %[[TRUE:[0-9a-zA-Z._-]+]](0x40000000),
> -; CHECK: %[[FALSE:[0-9a-zA-Z._-]+]](0x40000000)
> +; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
> +; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)
> ;
> ; Check that we emit the correct branch.
> -; CHECK: [[ADDR:%.*]](p0) = COPY %x0
> ; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
> ; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
> ; CHECK: G_BR %[[FALSE]]
> @@ -104,6 +111,7 @@ false:
> ; CHECK-LABEL: name: ori64
> ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> @@ -115,6 +123,7 @@ define i64 @ori64(i64 %arg1, i64 %arg2)
> ; CHECK-LABEL: name: ori32
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -127,6 +136,7 @@ define i32 @ori32(i32 %arg1, i32 %arg2)
> ; CHECK-LABEL: name: xori64
> ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> @@ -138,6 +148,7 @@ define i64 @xori64(i64 %arg1, i64 %arg2)
> ; CHECK-LABEL: name: xori32
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -150,6 +161,7 @@ define i32 @xori32(i32 %arg1, i32 %arg2)
> ; CHECK-LABEL: name: andi64
> ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> @@ -161,6 +173,7 @@ define i64 @andi64(i64 %arg1, i64 %arg2)
> ; CHECK-LABEL: name: andi32
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -173,6 +186,7 @@ define i32 @andi32(i32 %arg1, i32 %arg2)
> ; CHECK-LABEL: name: subi64
> ; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %x0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %x0
> @@ -184,6 +198,7 @@ define i64 @subi64(i64 %arg1, i64 %arg2)
> ; CHECK-LABEL: name: subi32
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -383,8 +398,8 @@ next:
> }
>
> ; CHECK-LABEL: name: constant_int_start
> -; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
> ; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2
> +; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
> ; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]]
> define i32 @constant_int_start() {
> %res = add i32 2, 42
> @@ -436,6 +451,7 @@ define i64 @test_zext(i32 %in) {
> ; CHECK-LABEL: name: test_shl
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -448,6 +464,7 @@ define i32 @test_shl(i32 %arg1, i32 %arg
> ; CHECK-LABEL: name: test_lshr
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -459,6 +476,7 @@ define i32 @test_lshr(i32 %arg1, i32 %ar
> ; CHECK-LABEL: name: test_ashr
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -470,6 +488,7 @@ define i32 @test_ashr(i32 %arg1, i32 %ar
> ; CHECK-LABEL: name: test_sdiv
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -481,6 +500,7 @@ define i32 @test_sdiv(i32 %arg1, i32 %ar
> ; CHECK-LABEL: name: test_udiv
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -492,6 +512,7 @@ define i32 @test_udiv(i32 %arg1, i32 %ar
> ; CHECK-LABEL: name: test_srem
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -503,6 +524,7 @@ define i32 @test_srem(i32 %arg1, i32 %ar
> ; CHECK-LABEL: name: test_urem
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %w0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %w0
> @@ -554,6 +576,7 @@ define void @int_comparison(i32 %a, i32
> ; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
> ; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
> ; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
> +; CHECK: bb.1:
> ; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
> ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
> define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
> @@ -565,6 +588,7 @@ define void @ptr_comparison(i8* %a, i8*
> ; CHECK-LABEL: name: test_fadd
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %s0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %s0
> @@ -576,6 +600,7 @@ define float @test_fadd(float %arg1, flo
> ; CHECK-LABEL: name: test_fsub
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %s0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %s0
> @@ -587,6 +612,7 @@ define float @test_fsub(float %arg1, flo
> ; CHECK-LABEL: name: test_fmul
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %s0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %s0
> @@ -598,6 +624,7 @@ define float @test_fmul(float %arg1, flo
> ; CHECK-LABEL: name: test_fdiv
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %s0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %s0
> @@ -609,6 +636,7 @@ define float @test_fdiv(float %arg1, flo
> ; CHECK-LABEL: name: test_frem
> ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
> ; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
> +; CHECK: bb.1:
> ; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]]
> ; CHECK-NEXT: %s0 = COPY [[RES]]
> ; CHECK-NEXT: RET_ReallyLR implicit %s0
> @@ -929,14 +957,18 @@ define void @test_large_const(i128* %add
>
> ; When there was no formal argument handling (so the first BB was empty) we used
> ; to insert the constants at the end of the block, even if they were encountered
> -; after the block's terminators had been emitted.
> -define i32 @test_const_placement() {
> +; after the block's terminators had been emitted. Also make sure the order is
> +; correct.
> +define i8* @test_const_placement() {
> ; CHECK-LABEL: name: test_const_placement
> -; CHECK: [[VAL:%[0-9]+]](s32) = G_CONSTANT i32 42
> -; CHECK: G_BR
> -
> +; CHECK: bb.0:
> +; CHECK: [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
> +; CHECK: bb.1:
> +; CHECK: G_BR
> +; CHECK: bb.2:
> +; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
> br label %next
>
> next:
> - ret i32 42
> + ret i8* inttoptr(i32 42 to i8*)
> }
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll Wed Dec 7 15:05:38 2016
> @@ -18,8 +18,8 @@ define signext i8 @test_stack_slots([8 x
> }
>
> ; CHECK-LABEL: name: test_call_stack
> -; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
> ; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42
> +; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
> ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
> ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
> ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator.ll Wed Dec 7 15:05:38 2016
> @@ -162,9 +162,9 @@ define void @test_stack_slots([8 x i64],
> }
>
> ; CHECK-LABEL: name: test_call_stack
> -; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
> -; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
> ; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
> +; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
> +; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
> ; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
> ; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
> ; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
>
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll Wed Dec 7 15:05:38 2016
> @@ -9,14 +9,15 @@ declare i32 @llvm.eh.typeid.for(i8*)
> ; CHECK: name: bar
> ; CHECK: body:
> ; CHECK: bb.0:
> -; CHECK: successors: %bb.2{{.*}}%bb.1
> +; CHECK: bb.1:
> +; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
> ; CHECK: EH_LABEL
> ; CHECK: %w0 = COPY
> ; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
> ; CHECK: {{%[0-9]+}}(s32) = COPY %w0
> ; CHECK: EH_LABEL
>
> -; CHECK: bb.1
> +; CHECK: [[BAD]] (landing-pad):
> ; CHECK: EH_LABEL
> ; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0
> ; CHECK: [[SEL:%[0-9]+]](p0) = COPY %x1
> @@ -25,7 +26,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
> ; CHECK: %x0 = COPY [[PTR_RET]]
> ; CHECK: %w1 = COPY [[SEL_RET]]
>
> -; CHECK: bb.2:
> +; CHECK: [[GOOD]]:
> ; CHECK: [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1
> ; CHECK: {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}(s128), [[SEL]](s32), 64
>
>
> Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll?rev=288980&r1=288979&r2=288980&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll Wed Dec 7 15:05:38 2016
> @@ -25,6 +25,8 @@ define void @test_void_return() {
> ; CHECK-NEXT: hasMustTailInVarArgFunc: false
> ; CHECK-NEXT: body:
> ; CHECK-NEXT: bb.0:
> +; CHECK-NEXT: successors: %bb.1(0x80000000)
> +; CHECK: bb.1:
> ; CHECK-NEXT: RET 0
> entry:
> ret void
>
>
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