[llvm] r288964 - [X86] Do not assume "ri" instructions always have an immediate operand

[Michael Kuperstein via llvm-commits]

Author: mkuper
Date: Wed Dec  7 13:29:18 2016
New Revision: 288964

URL: http://llvm.org/viewvc/llvm-project?rev=288964&view=rev
Log:
[X86] Do not assume "ri" instructions always have an immediate operand

The second operand of an "ri" instruction may be an immediate, but it may
also be a globalvariable, so we should make any assumptions.

This fixes PR31271.

Differential Revision: https://reviews.llvm.org/D27481

Added:
    llvm/trunk/test/CodeGen/X86/pr31271.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrBuilder.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=288964&r1=288963&r2=288964&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Wed Dec  7 13:29:18 2016
@@ -145,6 +145,11 @@ addOffset(const MachineInstrBuilder &MIB
   return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
 }
 
+static inline const MachineInstrBuilder &
+addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
+  return MIB.addImm(1).addReg(0).addOperand(Offset).addReg(0);
+}
+
 /// addRegOffset - This function is used to add a memory reference of the form
 /// [Reg + Offset], i.e., one with no scale or index, but with a
 /// displacement. An example is: DWORD PTR [EAX + 4].

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=288964&r1=288963&r2=288964&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Dec  7 13:29:18 2016
@@ -3878,7 +3878,7 @@ X86InstrInfo::convertToThreeAddress(Mach
     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
                           .addOperand(Dest)
                           .addOperand(Src),
-                      MI.getOperand(2).getImm());
+                      MI.getOperand(2));
     break;
   case X86::ADD32ri:
   case X86::ADD32ri8:
@@ -3901,7 +3901,7 @@ X86InstrInfo::convertToThreeAddress(Mach
     if (ImplicitOp.getReg() != 0)
       MIB.addOperand(ImplicitOp);
 
-    NewMI = addOffset(MIB, MI.getOperand(2).getImm());
+    NewMI = addOffset(MIB, MI.getOperand(2));
     break;
   }
   case X86::ADD16ri:
@@ -3915,7 +3915,7 @@ X86InstrInfo::convertToThreeAddress(Mach
     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
                           .addOperand(Dest)
                           .addOperand(Src),
-                      MI.getOperand(2).getImm());
+                      MI.getOperand(2));
     break;
   }
 

Added: llvm/trunk/test/CodeGen/X86/pr31271.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr31271.ll?rev=288964&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr31271.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr31271.ll Wed Dec  7 13:29:18 2016
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=i386-unknown-linux-gnu < %s | FileCheck %s
+
+ at c = external global [1 x i32], align 4
+
+; CHECK-LABEL: fn1
+; CHECK: leal c(%eax), %ecx
+define void @fn1(i32 %k) {
+  %g = getelementptr inbounds [1 x i32], [1 x i32]* @c, i32 0, i32 %k
+  %cmp = icmp ne i32* undef, %g
+  %z = zext i1 %cmp to i32
+  store i32 %z, i32* undef, align 4
+  %cmp2 = icmp eq i32* %g, null
+  br i1 %cmp2, label %u, label %r
+
+u:
+  unreachable
+
+r:
+  ret void
+}