[PATCH] D27461: [DAGCombine] Add (sext_in_reg (zext x)) -> (sext x) combine

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7130-7148
   // fold (sext_in_reg (sext x)) -> (sext x)
   // fold (sext_in_reg (aext x)) -> (sext x)
   // if x is small enough.
   if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
     SDValue N00 = N0.getOperand(0);
     if (N00.getScalarValueSizeInBits() <= EVTBits &&
         (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
----------------
RKSimon wrote:
> andreadb wrote:
> > Your new rule has a lot in common with the folding rules between lines [7130:7138]. You could potentially extend those folding rules to accomodate your extra case (ISD::ZERO_EXTEND). The only difference seems to be the check for EVTBits. All other checks (for legal operations) are identical.
> > 
> Thanks Andrea, I did try to merge the two but I the extra EVTBits logic just made it difficult to grok. 
Ah I see. I think it is fine then.

LGTM.

Thanks!


Repository:
  rL LLVM

https://reviews.llvm.org/D27461