[PATCH] D27395: Fixed store operation for a vector of i1.

[Elena Demikhovsky via Phabricator via llvm-commits]

delena added a comment.

In https://reviews.llvm.org/D27395#613711, @efriedma wrote:

> If you're going to put padding into `<4 x i1>` vectors, you're going to have to change the IR to match; getStoreSizeInBits() is currently 4 for `<4 x i1>`.


I agree, I'll need to take care for many aspects. I'll, probably, need to fix lowering of "bitcast <4 x i1> to i4".
The getStoreSizeInBits() will return 32. getSizeInBits() will return 4. But we have the same problem in the bit-packed variant.

> If we wanted bit-packed vectors, we could just ban masked.store for vectors whose elements aren't byte-aligned.

We can ban masked.store for i1 vectors, but I'm afraid that scalarization for the regular non-masked "store" will become impossible or will require load-modify-store sequence.
That's why I'd prefer to write bytes instead of bits.


Repository:
  rL LLVM

https://reviews.llvm.org/D27395