[llvm] r288657 - [AMDGPU] Disassembler: fix s_buffer_store_dword instructions
Sam Kolton via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 5 01:58:52 PST 2016
Author: skolton
Date: Mon Dec 5 03:58:51 2016
New Revision: 288657
URL: http://llvm.org/viewvc/llvm-project?rev=288657&view=rev
Log:
[AMDGPU] Disassembler: fix s_buffer_store_dword instructions
Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail.
Reviewers: tstellarAMD, vpykhtin, artem.tamazov
Subscribers: arsenm, nhaehnle, rampitec
Differential Revision: https://reviews.llvm.org/D27100
Modified:
llvm/trunk/lib/Target/AMDGPU/SMInstructions.td
llvm/trunk/test/MC/AMDGPU/smem.s
llvm/trunk/test/MC/Disassembler/AMDGPU/smem_vi.txt
Modified: llvm/trunk/lib/Target/AMDGPU/SMInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SMInstructions.td?rev=288657&r1=288656&r2=288657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SMInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SMInstructions.td Mon Dec 5 03:58:51 2016
@@ -394,16 +394,24 @@ multiclass SM_Real_Loads_vi<bits<8> op,
}
}
+class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
+ // encoding
+ bits<7> sdata;
+
+ let sdst = ?;
+ let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
+}
+
multiclass SM_Real_Stores_vi<bits<8> op, string ps,
SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
// FIXME: The operand name $offset is inconsistent with $soff used
// in the pseudo
- def _IMM_vi : SMEM_Real_vi <op, immPs> {
+ def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
}
- def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
+ def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
}
}
@@ -427,6 +435,7 @@ defm S_BUFFER_STORE_DWORD : SM_Real_S
defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
+// These instructions use same encoding
def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
Modified: llvm/trunk/test/MC/AMDGPU/smem.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smem.s?rev=288657&r1=288656&r2=288657&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smem.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smem.s Mon Dec 5 03:58:51 2016
@@ -1,35 +1,38 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSICI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=NOSICI %s
s_dcache_wb
// VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
-// NOSI: error: instruction not supported on this GPU
+// NOSICI: error: instruction not supported on this GPU
s_dcache_wb_vol
// VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
-// NOSI: error: instruction not supported on this GPU
+// NOSICI: error: instruction not supported on this GPU
s_memrealtime s[4:5]
// VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
-// NOSI: error: instruction not supported on this GPU
+// NOSICI: error: instruction not supported on this GPU
// FIXME: Should error about instruction on GPU
s_store_dword s1, s[2:3], 0xfc
// VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
-// NOSI: error: instruction not supported on this GPU
+// NOSICI: error: instruction not supported on this GPU
s_store_dword s1, s[2:3], 0xfc glc
// VI: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
-// NOSI: error: invalid operand for instruction
+// NOSICI: error: invalid operand for instruction
s_store_dword s1, s[2:3], s4
// VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
-// NOSI: error: instruction not supported on this GPU
+// NOSICI: error: instruction not supported on this GPU
s_store_dword s1, s[2:3], s4 glc
// VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
-// NOSI: error: invalid operand for instruction
+// NOSICI: error: invalid operand for instruction
// FIXME: Should error on SI instead of silently ignoring glc
s_load_dword s1, s[2:3], 0xfc glc
@@ -37,3 +40,27 @@ s_load_dword s1, s[2:3], 0xfc glc
s_load_dword s1, s[2:3], s4 glc
// VI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
+
+s_buffer_store_dword s10, s[92:95], m0
+// VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_buffer_store_dwordx2 s[10:11], s[92:95], m0
+// VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: instruction not supported on this GPU
+
+s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc
+// VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
+// NOSICI: error: invalid operand for instruction
+
+s_buffer_load_dword s10, s[92:95], m0
+// VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[92:95], m0
+// VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
+// SICI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0x7c,0x5c,0x45,0xc2]
+
+// FIXME: Should error on SI instead of silently ignoring glc
+s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
+// VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/smem_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/smem_vi.txt?rev=288657&r1=288656&r2=288657&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/smem_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/smem_vi.txt Mon Dec 5 03:58:51 2016
@@ -8,3 +8,39 @@
# VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
0x00 0x01 0x94 0xc0 0x00 0x00 0x00 0x00
+
+# VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
+0x41 0x00 0x42 0xc0 0xfc 0x00 0x00 0x00
+
+# VI: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
+0x41 0x00 0x43 0xc0 0xfc 0x00 0x00 0x00
+
+# VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
+0x41 0x00 0x40 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
+0x41 0x00 0x41 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
+0x41 0x00 0x03 0xc0 0xfc 0x00 0x00 0x00
+
+# VI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
+0x41 0x00 0x01 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
+0xae 0x02 0x60 0xc0 0x7c 0x00 0x00 0x00
+
+# VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
+0xae 0x02 0x64 0xc0 0x7c 0x00 0x00 0x00
+
+# VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
+0x2e 0x02 0x69 0xc0 0x7c 0x00 0x00 0x00
+
+# VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
+0xae 0x02 0x20 0xc0 0x7c 0x00 0x00 0x00
+
+# VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
+0xae 0x02 0x24 0xc0 0x7c 0x00 0x00 0x00
+
+# VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
+0x2e 0x02 0x29 0xc0 0x7c 0x00 0x00 0x00
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