[PATCH] D27401: [X86] Remove scalar logical op alias instructions. Just use COPY_FROM/TO_REGCLASS and the normal packed instructions instead

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, zvi, delena, RKSimon.
craig.topper added a subscriber: llvm-commits.

This patch removes the scalar logical operation alias instructions. We can just use reg class copies and use the normal packed instructions instead. This removes the need for putting these instructions in the execution domain fixing tables as was done recently.

I removed the loadf64_128 and loadf32_128 patterns as DAG combine creates a narrower load for (extractelt (loadv4f32)) before we ever get to isel.

I plan to add similar patterns for AVX512DQ in a future commit to allow use of the larger register class when available.


https://reviews.llvm.org/D27401

Files:
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/X86/sqrt-fastmath-mir.ll

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