[PATCH] D27395: Fixed store operation for a vector of i1.

[Elena Demikhovsky via Phabricator via llvm-commits]

delena added a comment.

In https://reviews.llvm.org/D27395#612972, @hfinkel wrote:

> Is that what we decided we wanted? I thought that we decided that we wanted i1 vectors to be bit packed?


I remember. First of all, the current implementation scalarizes store and just writes all bits to the same place, because Stride=0.
The same bug, btw, we have in scalarized load. I did not find how to reproduce it yet.

The second issue is the "masked store" of a vector of i1. Theoretically, if we do not support a masked operation, it should be scalarized.
 If we store a vector of bits, we should do load-modify-store. Is this operation allowed in terms of multithreading?
Masked and unmasked store should be compatible.

As far as AVX-512 mask registers, spill-fill should be done in bits, using KMOV.


Repository:
  rL LLVM

https://reviews.llvm.org/D27395