[PATCH] D27395: Fixed store operation for a vector of i1.

[Elena Demikhovsky via Phabricator via llvm-commits]

delena added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:3298
   unsigned Stride = MemSclVT.getSizeInBits() / 8;
+  Stride = (Stride == 0) ? 1 : Stride; // Stride can't be less than 1 byte.
   EVT IdxVT = getVectorIdxTy(DAG.getDataLayout());
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craig.topper wrote:
> Should this just be
> 
> unsigned Stride = (MemSclVT.getSizeInBits() + 7) / 8;
> 
> So that it always rounds up to the next byte for any size that isn't divisible by 8?
May be. But it will never be called with i9 or i541. It is power of 2.


Repository:
  rL LLVM

https://reviews.llvm.org/D27395