[llvm] r288526 - [SystemZ] Support remaining atomic instructions
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 2 10:24:16 PST 2016
Author: uweigand
Date: Fri Dec 2 12:24:16 2016
New Revision: 288526
URL: http://llvm.org/viewvc/llvm-project?rev=288526&view=rev
Log:
[SystemZ] Support remaining atomic instructions
Add assembler support for all atomic instructions that weren't already
supported. Some of those could be used to implement codegen for 128-bit
atomic operations, but this isn't done here yet.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good-z196.s
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Fri Dec 2 12:24:16 2016
@@ -833,6 +833,23 @@ class InstSSd<bits<8> op, dag outs, dag
let Inst{15-0} = BD2;
}
+class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<6, outs, ins, asmstr, pattern> {
+ field bits<48> Inst;
+ field bits<48> SoftFail = 0;
+
+ bits<4> R1;
+ bits<16> BD2;
+ bits<4> R3;
+ bits<16> BD4;
+
+ let Inst{47-40} = op;
+ let Inst{39-36} = R1;
+ let Inst{35-32} = R3;
+ let Inst{31-16} = BD2;
+ let Inst{15-0} = BD4;
+}
+
class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
@@ -2872,6 +2889,12 @@ multiclass BinarySIPair<string mnemonic,
}
}
+class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
+ : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
+ mnemonic#"\t$R3, $BD1, $BD2", []> {
+ let mayLoad = 1;
+}
+
class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
TypedReg tr, bits<4> type>
: InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
@@ -3611,6 +3634,12 @@ multiclass QuaternaryOptVRRdSPairGeneric
VR128:$V4, imm32zx4:$M5, 0)>;
}
+class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
+ RegisterOperand cls>
+ : InstSSe<opcode, (outs),
+ (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
+ mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
+
class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, AddressingMode mode = bdaddr20only>
: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Fri Dec 2 12:24:16 2016
@@ -1546,11 +1546,40 @@ def ATOMIC_CMP_SWAPW
let hasNoSchedulingInfo = 1;
}
+// Test and set.
+let mayLoad = 1, Defs = [CC] in
+ def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>;
+
+// Compare and swap.
let Defs = [CC] in {
defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
}
+// Compare double and swap.
+let Defs = [CC] in {
+ defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>;
+ def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, null_frag, GR128>;
+}
+
+// Compare and swap and store.
+let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in
+ def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>;
+
+// Perform locked operation.
+let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in
+ def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>;
+
+// Load/store pair from/to quadword.
+def LPQ : UnaryRXY<"lpq", 0xE38F, null_frag, GR128, 16>;
+def STPQ : StoreRXY<"stpq", 0xE38E, null_frag, GR128, 16>;
+
+// Load pair disjoint.
+let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
+ def LPD : BinarySSF<"lpd", 0xC84, GR128>;
+ def LPDG : BinarySSF<"lpdg", 0xC85, GR128>;
+}
+
//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td Fri Dec 2 12:24:16 2016
@@ -537,9 +537,31 @@ def : InstRW<[FXb, LSU, Lat5], (instrege
def : InstRW<[FXb, LSU, Lat5], (instregex "LAO(G)?$")>;
def : InstRW<[FXb, LSU, Lat5], (instregex "LAX(G)?$")>;
+// Test and set
+def : InstRW<[FXb, LSU, Lat5, EndGroup], (instregex "TS$")>;
+
// Compare and swap
def : InstRW<[FXa, FXb, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
+// Compare double and swap
+def : InstRW<[FXa, FXa, FXb, FXb, FXa, LSU, Lat10, GroupAlone],
+ (instregex "CDS(Y)?$")>;
+def : InstRW<[FXa, FXa, FXb, FXb, LSU, FXb, FXb, LSU, LSU, Lat20, GroupAlone],
+ (instregex "CDSG$")>;
+
+// Compare and swap and store
+def : InstRW<[FXa, Lat30, GroupAlone], (instregex "CSST$")>;
+
+// Perform locked operation
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
+
+// Load/store pair from/to quadword
+def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
+def : InstRW<[FXb, FXb, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
+
+// Load pair disjoint
+def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
+
//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td Fri Dec 2 12:24:16 2016
@@ -494,9 +494,31 @@ def : InstRW<[FXU, LSU, Lat5], (instrege
def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
+// Test and set
+def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
+
// Compare and swap
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
+// Compare double and swap
+def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
+ (instregex "CDS(Y)?$")>;
+def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
+ (instregex "CDSG$")>;
+
+// Compare and swap and store
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
+
+// Perform locked operation
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
+
+// Load/store pair from/to quadword
+def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
+def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
+
+// Load pair disjoint
+def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
+
//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td Fri Dec 2 12:24:16 2016
@@ -506,9 +506,31 @@ def : InstRW<[FXU, LSU, Lat5], (instrege
def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
+// Test and set
+def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
+
// Compare and swap
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
+// Compare double and swap
+def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
+ (instregex "CDS(Y)?$")>;
+def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
+ (instregex "CDSG$")>;
+
+// Compare and swap and store
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
+
+// Perform locked operation
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
+
+// Load/store pair from/to quadword
+def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
+def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
+
+// Load pair disjoint
+def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
+
//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Fri Dec 2 12:24:16 2016
@@ -1342,6 +1342,96 @@
# CHECK: cdlgbr %f15, 0, %r0, 1
0xb3 0xa1 0x01 0xf0
+# CHECK: cds %r0, %r0, 0
+0xbb 0x00 0x00 0x00
+
+# CHECK: cds %r0, %r0, 4095
+0xbb 0x00 0x0f 0xff
+
+# CHECK: cds %r0, %r0, 0(%r1)
+0xbb 0x00 0x10 0x00
+
+# CHECK: cds %r0, %r0, 0(%r15)
+0xbb 0x00 0xf0 0x00
+
+# CHECK: cds %r0, %r0, 4095(%r1)
+0xbb 0x00 0x1f 0xff
+
+# CHECK: cds %r0, %r0, 4095(%r15)
+0xbb 0x00 0xff 0xff
+
+# CHECK: cds %r0, %r14, 0
+0xbb 0x0e 0x00 0x00
+
+# CHECK: cds %r14, %r0, 0
+0xbb 0xe0 0x00 0x00
+
+# CHECK: cdsg %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0x3e
+
+# CHECK: cdsg %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0x3e
+
+# CHECK: cdsg %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0x3e
+
+# CHECK: cdsg %r0, %r0, 1
+0xeb 0x00 0x00 0x01 0x00 0x3e
+
+# CHECK: cdsg %r0, %r0, 524287
+0xeb 0x00 0x0f 0xff 0x7f 0x3e
+
+# CHECK: cdsg %r0, %r0, 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0x3e
+
+# CHECK: cdsg %r0, %r0, 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0x3e
+
+# CHECK: cdsg %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0x3e
+
+# CHECK: cdsg %r0, %r0, 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0x3e
+
+# CHECK: cdsg %r0, %r14, 0
+0xeb 0x0e 0x00 0x00 0x00 0x3e
+
+# CHECK: cdsg %r14, %r0, 0
+0xeb 0xe0 0x00 0x00 0x00 0x3e
+
+# CHECK: cdsy %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0x31
+
+# CHECK: cdsy %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0x31
+
+# CHECK: cdsy %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0x31
+
+# CHECK: cdsy %r0, %r0, 1
+0xeb 0x00 0x00 0x01 0x00 0x31
+
+# CHECK: cdsy %r0, %r0, 524287
+0xeb 0x00 0x0f 0xff 0x7f 0x31
+
+# CHECK: cdsy %r0, %r0, 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0x31
+
+# CHECK: cdsy %r0, %r0, 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0x31
+
+# CHECK: cdsy %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0x31
+
+# CHECK: cdsy %r0, %r0, 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0x31
+
+# CHECK: cdsy %r0, %r14, 0
+0xeb 0x0e 0x00 0x00 0x00 0x31
+
+# CHECK: cdsy %r14, %r0, 0
+0xeb 0xe0 0x00 0x00 0x00 0x31
+
# CHECK: cebr %f0, %f0
0xb3 0x09 0x00 0x00
@@ -3451,6 +3541,27 @@
# CHECK: csy %r15, %r0, 0
0xeb 0xf0 0x00 0x00 0x00 0x14
+# CHECK: csst 0, 0, %r0
+0xc8 0x02 0x00 0x00 0x00 0x00
+
+# CHECK: csst 0, 4095, %r2
+0xc8 0x22 0x00 0x00 0x0f 0xff
+
+# CHECK: csst 0, 0(%r1), %r2
+0xc8 0x22 0x00 0x00 0x10 0x00
+
+# CHECK: csst 0, 0(%r15), %r2
+0xc8 0x22 0x00 0x00 0xf0 0x00
+
+# CHECK: csst 0(%r1), 4095(%r15), %r2
+0xc8 0x22 0x10 0x00 0xff 0xff
+
+# CHECK: csst 0(%r1), 0(%r15), %r2
+0xc8 0x22 0x10 0x00 0xf0 0x00
+
+# CHECK: csst 4095(%r1), 0(%r15), %r2
+0xc8 0x22 0x1f 0xff 0xf0 0x00
+
# CHECK: c %r0, 0
0x59 0x00 0x00 0x00
@@ -6442,6 +6553,48 @@
# CHECK: locgr %r11, %r3, 15
0xb9 0xe2 0xf0 0xb3
+# CHECK: lpd %r0, 0, 0
+0xc8 0x04 0x00 0x00 0x00 0x00
+
+# CHECK: lpd %r2, 0, 4095
+0xc8 0x24 0x00 0x00 0x0f 0xff
+
+# CHECK: lpd %r2, 0, 0(%r1)
+0xc8 0x24 0x00 0x00 0x10 0x00
+
+# CHECK: lpd %r2, 0, 0(%r15)
+0xc8 0x24 0x00 0x00 0xf0 0x00
+
+# CHECK: lpd %r2, 0(%r1), 4095(%r15)
+0xc8 0x24 0x10 0x00 0xff 0xff
+
+# CHECK: lpd %r2, 0(%r1), 0(%r15)
+0xc8 0x24 0x10 0x00 0xf0 0x00
+
+# CHECK: lpd %r2, 4095(%r1), 0(%r15)
+0xc8 0x24 0x1f 0xff 0xf0 0x00
+
+# CHECK: lpdg %r0, 0, 0
+0xc8 0x05 0x00 0x00 0x00 0x00
+
+# CHECK: lpdg %r2, 0, 4095
+0xc8 0x25 0x00 0x00 0x0f 0xff
+
+# CHECK: lpdg %r2, 0, 0(%r1)
+0xc8 0x25 0x00 0x00 0x10 0x00
+
+# CHECK: lpdg %r2, 0, 0(%r15)
+0xc8 0x25 0x00 0x00 0xf0 0x00
+
+# CHECK: lpdg %r2, 0(%r1), 4095(%r15)
+0xc8 0x25 0x10 0x00 0xff 0xff
+
+# CHECK: lpdg %r2, 0(%r1), 0(%r15)
+0xc8 0x25 0x10 0x00 0xf0 0x00
+
+# CHECK: lpdg %r2, 4095(%r1), 0(%r15)
+0xc8 0x25 0x1f 0xff 0xf0 0x00
+
# CHECK: lpdbr %f0, %f9
0xb3 0x10 0x00 0x09
@@ -6502,6 +6655,36 @@
# CHECK: lpr %r7, %r8
0x10 0x78
+# CHECK: lpq %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x8f
+
+# CHECK: lpq %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x8f
+
+# CHECK: lpq %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x8f
+
+# CHECK: lpq %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x8f
+
+# CHECK: lpq %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x8f
+
+# CHECK: lpq %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x8f
+
+# CHECK: lpq %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x8f
+
+# CHECK: lpq %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x8f
+
+# CHECK: lpq %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x8f
+
+# CHECK: lpq %r14, 0
+0xe3 0xe0 0x00 0x00 0x00 0x8f
+
# CHECK: lpxbr %f0, %f8
0xb3 0x40 0x00 0x08
@@ -8395,6 +8578,27 @@
# CHECK: pfd 15, 0
0xe3 0xf0 0x00 0x00 0x00 0x36
+# CHECK: plo %r0, 0, %r0, 0
+0xee 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: plo %r2, 0, %r4, 4095
+0xee 0x24 0x00 0x00 0x0f 0xff
+
+# CHECK: plo %r2, 0, %r4, 0(%r1)
+0xee 0x24 0x00 0x00 0x10 0x00
+
+# CHECK: plo %r2, 0, %r4, 0(%r15)
+0xee 0x24 0x00 0x00 0xf0 0x00
+
+# CHECK: plo %r2, 0(%r1), %r4, 4095(%r15)
+0xee 0x24 0x10 0x00 0xff 0xff
+
+# CHECK: plo %r2, 0(%r1), %r4, 0(%r15)
+0xee 0x24 0x10 0x00 0xf0 0x00
+
+# CHECK: plo %r2, 4095(%r1), %r4, 0(%r15)
+0xee 0x24 0x1f 0xff 0xf0 0x00
+
# CHECK: pr
0x01 0x01
@@ -10528,6 +10732,36 @@
# CHECK: stocg %r1, 2(%r3), 15
0xeb 0x1f 0x30 0x02 0x00 0xe3
+# CHECK: stpq %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x8e
+
+# CHECK: stpq %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x8e
+
+# CHECK: stpq %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x8e
+
+# CHECK: stpq %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x8e
+
+# CHECK: stpq %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x8e
+
+# CHECK: stpq %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x8e
+
+# CHECK: stpq %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x8e
+
+# CHECK: stpq %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x8e
+
+# CHECK: stpq %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x8e
+
+# CHECK: stpq %r14, 0
+0xe3 0xe0 0x00 0x00 0x00 0x8e
+
# CHECK: s %r0, 0
0x5b 0x00 0x00 0x00
@@ -10885,6 +11119,24 @@
# CHECK: tmy 524287(%r15), 42
0xeb 0x2a 0xff 0xff 0x7f 0x51
+# CHECK: ts 0
+0x93 0x00 0x00 0x00
+
+# CHECK: ts 0(%r1)
+0x93 0x00 0x10 0x00
+
+#CHECK: ts 0(%r15)
+0x93 0x00 0xf0 0x00
+
+#CHECK: ts 4095
+0x93 0x00 0x0f 0xff
+
+#CHECK: ts 4095(%r1)
+0x93 0x00 0x1f 0xff
+
+#CHECK: ts 4095(%r15)
+0x93 0x00 0xff 0xff
+
# CHECK: xc 0(1), 0
0xd7 0x00 0x00 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Fri Dec 2 12:24:16 2016
@@ -762,6 +762,46 @@
niai 0, 0
+#CHECK: error: invalid register pair
+#CHECK: lpd %r1, 0, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: lpd %r2, 160(%r1,%r15), 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpd %r2, -1(%r1), 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpd %r2, 4096(%r1), 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpd %r2, 0(%r1), -1(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpd %r2, 0(%r1), 4096(%r15)
+
+ lpd %r1, 0, 0
+ lpd %r2, 160(%r1,%r15), 160(%r15)
+ lpd %r2, -1(%r1), 160(%r15)
+ lpd %r2, 4096(%r1), 160(%r15)
+ lpd %r2, 0(%r1), -1(%r15)
+ lpd %r2, 0(%r1), 4096(%r15)
+
+#CHECK: error: invalid register pair
+#CHECK: lpdg %r1, 0, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: lpdg %r2, 160(%r1,%r15), 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpdg %r2, -1(%r1), 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpdg %r2, 4096(%r1), 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpdg %r2, 0(%r1), -1(%r15)
+#CHECK: error: invalid operand
+#CHECK: lpdg %r2, 0(%r1), 4096(%r15)
+
+ lpdg %r1, 0, 0
+ lpdg %r2, 160(%r1,%r15), 160(%r15)
+ lpdg %r2, -1(%r1), 160(%r15)
+ lpdg %r2, 4096(%r1), 160(%r15)
+ lpdg %r2, 0(%r1), -1(%r15)
+ lpdg %r2, 0(%r1), 4096(%r15)
+
#CHECK: error: instruction requires: transactional-execution
#CHECK: ntstg %r0, 524287(%r1,%r15)
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Fri Dec 2 12:24:16 2016
@@ -553,6 +553,57 @@
cdlgbr %f0, 0, %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cds %r1, %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cds %r0, %r1, 0
+#CHECK: error: invalid operand
+#CHECK: cds %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: cds %r0, %r0, 4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: cds %r0, %r0, 0(%r1,%r2)
+
+ cds %r1, %r0, 0
+ cds %r0, %r1, 0
+ cds %r0, %r0, -1
+ cds %r0, %r0, 4096
+ cds %r0, %r0, 0(%r1,%r2)
+
+#CHECK: error: invalid register pair
+#CHECK: cdsg %r1, %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cdsg %r0, %r1, 0
+#CHECK: error: invalid operand
+#CHECK: cdsg %r0, %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: cdsg %r0, %r0, 524288
+#CHECK: error: invalid use of indexed addressing
+#CHECK: cdsg %r0, %r0, 0(%r1,%r2)
+
+ cdsg %r1, %r0, 0
+ cdsg %r0, %r1, 0
+ cdsg %r0, %r0, -524289
+ cdsg %r0, %r0, 524288
+ cdsg %r0, %r0, 0(%r1,%r2)
+
+#CHECK: error: invalid register pair
+#CHECK: cdsy %r1, %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cdsy %r0, %r1, 0
+#CHECK: error: invalid operand
+#CHECK: cdsy %r0, %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: cdsy %r0, %r0, 524288
+#CHECK: error: invalid use of indexed addressing
+#CHECK: cdsy %r0, %r0, 0(%r1,%r2)
+
+ cdsy %r1, %r0, 0
+ cdsy %r0, %r1, 0
+ cdsy %r0, %r0, -524289
+ cdsy %r0, %r0, 524288
+ cdsy %r0, %r0, 0(%r1,%r2)
+
#CHECK: error: invalid operand
#CHECK: ceb %f0, -1
#CHECK: error: invalid operand
@@ -1482,6 +1533,23 @@
csy %r0, %r0, 524288
csy %r0, %r0, 0(%r1,%r2)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: csst 160(%r1,%r15), 160(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: csst -1(%r1), 160(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: csst 4096(%r1), 160(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: csst 0(%r1), -1(%r15), %r2
+#CHECK: error: invalid operand
+#CHECK: csst 0(%r1), 4096(%r15), %r2
+
+ csst 160(%r1,%r15), 160(%r15), %r2
+ csst -1(%r1), 160(%r15), %r2
+ csst 4096(%r1), 160(%r15), %r2
+ csst 0(%r1), -1(%r15), %r2
+ csst 0(%r1), 4096(%r15), %r2
+
#CHECK: error: invalid register pair
#CHECK: cxbr %f0, %f2
#CHECK: error: invalid register pair
@@ -2365,6 +2433,25 @@
lnxbr %f0, %f2
lnxbr %f2, %f0
+#CHECK: error: instruction requires: interlocked-access1
+#CHECK: lpd %r0, 0, 0
+ lpd %r0, 0, 0
+
+#CHECK: error: instruction requires: interlocked-access1
+#CHECK: lpdg %r0, 0, 0
+ lpdg %r0, 0, 0
+
+#CHECK: error: invalid register pair
+#CHECK: lpq %r1, 0
+#CHECK: error: invalid operand
+#CHECK: lpq %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: lpq %r0, 524288
+
+ lpq %r1, 0
+ lpq %r0, -524289
+ lpq %r0, 524288
+
#CHECK: error: invalid register pair
#CHECK: lpxbr %f0, %f2
#CHECK: error: invalid register pair
@@ -3150,6 +3237,23 @@
pfdrl 1, 1
pfdrl 1, 0x100000000
+#CHECK: error: invalid use of indexed addressing
+#CHECK: plo %r2, 160(%r1,%r15), %r4, 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: plo %r2, -1(%r1), %r4, 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: plo %r2, 4096(%r1), %r4, 160(%r15)
+#CHECK: error: invalid operand
+#CHECK: plo %r2, 0(%r1), %r4, -1(%r15)
+#CHECK: error: invalid operand
+#CHECK: plo %r2, 0(%r1), %r4, 4096(%r15)
+
+ plo %r2, 160(%r1,%r15), %r4, 160(%r15)
+ plo %r2, -1(%r1), %r4, 160(%r15)
+ plo %r2, 4096(%r1), %r4, 160(%r15)
+ plo %r2, 0(%r1), %r4, -1(%r15)
+ plo %r2, 0(%r1), %r4, 4096(%r15)
+
#CHECK: error: instruction requires: population-count
#CHECK: popcnt %r0, %r0
@@ -3780,6 +3884,17 @@
stmy %r0, %r0, 524288
stmy %r0, %r0, 0(%r1,%r2)
+#CHECK: error: invalid register pair
+#CHECK: stpq %r1, 0
+#CHECK: error: invalid operand
+#CHECK: stpq %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: stpq %r0, 524288
+
+ stpq %r1, 0
+ stpq %r0, -524289
+ stpq %r0, 524288
+
#CHECK: error: invalid use of indexed addressing
#CHECK: strag 160(%r1,%r15),160(%r15)
#CHECK: error: invalid operand
@@ -3958,6 +4073,17 @@
tmy 0, 256
#CHECK: error: invalid operand
+#CHECK: ts -1
+#CHECK: error: invalid operand
+#CHECK: ts 4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: ts 0(%r1,%r2)
+
+ ts -1
+ ts 4096
+ ts 0(%r1,%r2)
+
+#CHECK: error: invalid operand
#CHECK: x %r0, -1
#CHECK: error: invalid operand
#CHECK: x %r0, 4096
Modified: llvm/trunk/test/MC/SystemZ/insn-good-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-z196.s?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-z196.s Fri Dec 2 12:24:16 2016
@@ -1227,6 +1227,34 @@
locrnp %r1,%r3
locrno %r1,%r3
+#CHECK: lpd %r0, 0, 0 # encoding: [0xc8,0x04,0x00,0x00,0x00,0x00]
+#CHECK: lpd %r2, 0(%r1), 0(%r15) # encoding: [0xc8,0x24,0x10,0x00,0xf0,0x00]
+#CHECK: lpd %r2, 1(%r1), 0(%r15) # encoding: [0xc8,0x24,0x10,0x01,0xf0,0x00]
+#CHECK: lpd %r2, 4095(%r1), 0(%r15) # encoding: [0xc8,0x24,0x1f,0xff,0xf0,0x00]
+#CHECK: lpd %r2, 0(%r1), 1(%r15) # encoding: [0xc8,0x24,0x10,0x00,0xf0,0x01]
+#CHECK: lpd %r2, 0(%r1), 4095(%r15) # encoding: [0xc8,0x24,0x10,0x00,0xff,0xff]
+
+ lpd %r0, 0, 0
+ lpd %r2, 0(%r1), 0(%r15)
+ lpd %r2, 1(%r1), 0(%r15)
+ lpd %r2, 4095(%r1), 0(%r15)
+ lpd %r2, 0(%r1), 1(%r15)
+ lpd %r2, 0(%r1), 4095(%r15)
+
+#CHECK: lpdg %r0, 0, 0 # encoding: [0xc8,0x05,0x00,0x00,0x00,0x00]
+#CHECK: lpdg %r2, 0(%r1), 0(%r15) # encoding: [0xc8,0x25,0x10,0x00,0xf0,0x00]
+#CHECK: lpdg %r2, 1(%r1), 0(%r15) # encoding: [0xc8,0x25,0x10,0x01,0xf0,0x00]
+#CHECK: lpdg %r2, 4095(%r1), 0(%r15) # encoding: [0xc8,0x25,0x1f,0xff,0xf0,0x00]
+#CHECK: lpdg %r2, 0(%r1), 1(%r15) # encoding: [0xc8,0x25,0x10,0x00,0xf0,0x01]
+#CHECK: lpdg %r2, 0(%r1), 4095(%r15) # encoding: [0xc8,0x25,0x10,0x00,0xff,0xff]
+
+ lpdg %r0, 0, 0
+ lpdg %r2, 0(%r1), 0(%r15)
+ lpdg %r2, 1(%r1), 0(%r15)
+ lpdg %r2, 4095(%r1), 0(%r15)
+ lpdg %r2, 0(%r1), 1(%r15)
+ lpdg %r2, 0(%r1), 4095(%r15)
+
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=288526&r1=288525&r2=288526&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Fri Dec 2 12:24:16 2016
@@ -1849,6 +1849,72 @@
cdgbr %f7, %r8
cdgbr %f15, %r15
+#CHECK: cds %r0, %r0, 0 # encoding: [0xbb,0x00,0x00,0x00]
+#CHECK: cds %r0, %r0, 4095 # encoding: [0xbb,0x00,0x0f,0xff]
+#CHECK: cds %r0, %r0, 0(%r1) # encoding: [0xbb,0x00,0x10,0x00]
+#CHECK: cds %r0, %r0, 0(%r15) # encoding: [0xbb,0x00,0xf0,0x00]
+#CHECK: cds %r0, %r0, 4095(%r1) # encoding: [0xbb,0x00,0x1f,0xff]
+#CHECK: cds %r0, %r0, 4095(%r15) # encoding: [0xbb,0x00,0xff,0xff]
+#CHECK: cds %r0, %r14, 0 # encoding: [0xbb,0x0e,0x00,0x00]
+#CHECK: cds %r14, %r0, 0 # encoding: [0xbb,0xe0,0x00,0x00]
+
+ cds %r0, %r0, 0
+ cds %r0, %r0, 4095
+ cds %r0, %r0, 0(%r1)
+ cds %r0, %r0, 0(%r15)
+ cds %r0, %r0, 4095(%r1)
+ cds %r0, %r0, 4095(%r15)
+ cds %r0, %r14, 0
+ cds %r14, %r0, 0
+
+#CHECK: cdsg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x3e]
+#CHECK: cdsg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x3e]
+#CHECK: cdsg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x3e]
+#CHECK: cdsg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x3e]
+#CHECK: cdsg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x3e]
+#CHECK: cdsg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x3e]
+#CHECK: cdsg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x3e]
+#CHECK: cdsg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x3e]
+#CHECK: cdsg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x3e]
+#CHECK: cdsg %r0, %r14, 0 # encoding: [0xeb,0x0e,0x00,0x00,0x00,0x3e]
+#CHECK: cdsg %r14, %r0, 0 # encoding: [0xeb,0xe0,0x00,0x00,0x00,0x3e]
+
+ cdsg %r0, %r0, -524288
+ cdsg %r0, %r0, -1
+ cdsg %r0, %r0, 0
+ cdsg %r0, %r0, 1
+ cdsg %r0, %r0, 524287
+ cdsg %r0, %r0, 0(%r1)
+ cdsg %r0, %r0, 0(%r15)
+ cdsg %r0, %r0, 524287(%r1)
+ cdsg %r0, %r0, 524287(%r15)
+ cdsg %r0, %r14, 0
+ cdsg %r14, %r0, 0
+
+#CHECK: cdsy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x31]
+#CHECK: cdsy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x31]
+#CHECK: cdsy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x31]
+#CHECK: cdsy %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x31]
+#CHECK: cdsy %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x31]
+#CHECK: cdsy %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x31]
+#CHECK: cdsy %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x31]
+#CHECK: cdsy %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x31]
+#CHECK: cdsy %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x31]
+#CHECK: cdsy %r0, %r14, 0 # encoding: [0xeb,0x0e,0x00,0x00,0x00,0x31]
+#CHECK: cdsy %r14, %r0, 0 # encoding: [0xeb,0xe0,0x00,0x00,0x00,0x31]
+
+ cdsy %r0, %r0, -524288
+ cdsy %r0, %r0, -1
+ cdsy %r0, %r0, 0
+ cdsy %r0, %r0, 1
+ cdsy %r0, %r0, 524287
+ cdsy %r0, %r0, 0(%r1)
+ cdsy %r0, %r0, 0(%r15)
+ cdsy %r0, %r0, 524287(%r1)
+ cdsy %r0, %r0, 524287(%r15)
+ cdsy %r0, %r14, 0
+ cdsy %r14, %r0, 0
+
#CHECK: ceb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x09]
#CHECK: ceb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x09]
#CHECK: ceb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x09]
@@ -5581,6 +5647,20 @@
csy %r0, %r15, 0
csy %r15, %r0, 0
+#CHECK: csst 0, 0, %r0 # encoding: [0xc8,0x02,0x00,0x00,0x00,0x00]
+#CHECK: csst 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xf0,0x00]
+#CHECK: csst 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x01,0xf0,0x00]
+#CHECK: csst 4095(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x1f,0xff,0xf0,0x00]
+#CHECK: csst 0(%r1), 1(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xf0,0x01]
+#CHECK: csst 0(%r1), 4095(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xff,0xff]
+
+ csst 0, 0, %r0
+ csst 0(%r1), 0(%r15), %r2
+ csst 1(%r1), 0(%r15), %r2
+ csst 4095(%r1), 0(%r15), %r2
+ csst 0(%r1), 1(%r15), %r2
+ csst 0(%r1), 4095(%r15), %r2
+
#CHECK: cxbr %f0, %f0 # encoding: [0xb3,0x49,0x00,0x00]
#CHECK: cxbr %f0, %f13 # encoding: [0xb3,0x49,0x00,0x0d]
#CHECK: cxbr %f8, %f8 # encoding: [0xb3,0x49,0x00,0x88]
@@ -7516,6 +7596,28 @@
lpgr %r15,%r0
lpgr %r7,%r8
+#CHECK: lpq %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x8f]
+#CHECK: lpq %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x8f]
+#CHECK: lpq %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x8f]
+#CHECK: lpq %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x8f]
+#CHECK: lpq %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x8f]
+#CHECK: lpq %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x8f]
+#CHECK: lpq %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x8f]
+#CHECK: lpq %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x8f]
+#CHECK: lpq %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x8f]
+#CHECK: lpq %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x8f]
+
+ lpq %r0, -524288
+ lpq %r0, -1
+ lpq %r0, 0
+ lpq %r0, 1
+ lpq %r0, 524287
+ lpq %r0, 0(%r1)
+ lpq %r0, 0(%r15)
+ lpq %r0, 524287(%r1,%r15)
+ lpq %r0, 524287(%r15,%r1)
+ lpq %r14, 0
+
#CHECK: lpr %r0, %r0 # encoding: [0x10,0x00]
#CHECK: lpr %r0, %r15 # encoding: [0x10,0x0f]
#CHECK: lpr %r15, %r0 # encoding: [0x10,0xf0]
@@ -8982,6 +9084,20 @@
pfdrl 7, frob at PLT
pfdrl 8, frob at PLT
+#CHECK: plo %r0, 0, %r0, 0 # encoding: [0xee,0x00,0x00,0x00,0x00,0x00]
+#CHECK: plo %r2, 0(%r1), %r4, 0(%r15) # encoding: [0xee,0x24,0x10,0x00,0xf0,0x00]
+#CHECK: plo %r2, 1(%r1), %r4, 0(%r15) # encoding: [0xee,0x24,0x10,0x01,0xf0,0x00]
+#CHECK: plo %r2, 4095(%r1), %r4, 0(%r15) # encoding: [0xee,0x24,0x1f,0xff,0xf0,0x00]
+#CHECK: plo %r2, 0(%r1), %r4, 1(%r15) # encoding: [0xee,0x24,0x10,0x00,0xf0,0x01]
+#CHECK: plo %r2, 0(%r1), %r4, 4095(%r15) # encoding: [0xee,0x24,0x10,0x00,0xff,0xff]
+
+ plo %r0, 0, %r0, 0
+ plo %r2, 0(%r1), %r4, 0(%r15)
+ plo %r2, 1(%r1), %r4, 0(%r15)
+ plo %r2, 4095(%r1), %r4, 0(%r15)
+ plo %r2, 0(%r1), %r4, 1(%r15)
+ plo %r2, 0(%r1), %r4, 4095(%r15)
+
#CHECK: pr # encoding: [0x01,0x01]
pr
@@ -10257,6 +10373,28 @@
stmy %r0,%r0,524287(%r1)
stmy %r0,%r0,524287(%r15)
+#CHECK: stpq %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x8e]
+#CHECK: stpq %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x8e]
+#CHECK: stpq %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x8e]
+#CHECK: stpq %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x8e]
+#CHECK: stpq %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x8e]
+#CHECK: stpq %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x8e]
+#CHECK: stpq %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x8e]
+#CHECK: stpq %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x8e]
+#CHECK: stpq %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x8e]
+#CHECK: stpq %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x8e]
+
+ stpq %r0, -524288
+ stpq %r0, -1
+ stpq %r0, 0
+ stpq %r0, 1
+ stpq %r0, 524287
+ stpq %r0, 0(%r1)
+ stpq %r0, 0(%r15)
+ stpq %r0, 524287(%r1,%r15)
+ stpq %r0, 524287(%r15,%r1)
+ stpq %r14, 0
+
#CHECK: strag 0, 0 # encoding: [0xe5,0x02,0x00,0x00,0x00,0x00]
#CHECK: strag 0(%r1), 0(%r2) # encoding: [0xe5,0x02,0x10,0x00,0x20,0x00]
#CHECK: strag 160(%r1), 320(%r15) # encoding: [0xe5,0x02,0x10,0xa0,0xf1,0x40]
@@ -10596,6 +10734,20 @@
tmy 524287(%r1), 42
tmy 524287(%r15), 42
+#CHECK: ts 0 # encoding: [0x93,0x00,0x00,0x00]
+#CHECK: ts 0(%r1) # encoding: [0x93,0x00,0x10,0x00]
+#CHECK: ts 0(%r15) # encoding: [0x93,0x00,0xf0,0x00]
+#CHECK: ts 4095 # encoding: [0x93,0x00,0x0f,0xff]
+#CHECK: ts 4095(%r1) # encoding: [0x93,0x00,0x1f,0xff]
+#CHECK: ts 4095(%r15) # encoding: [0x93,0x00,0xff,0xff]
+
+ ts 0
+ ts 0(%r1)
+ ts 0(%r15)
+ ts 4095
+ ts 4095(%r1)
+ ts 4095(%r15)
+
#CHECK: x %r0, 0 # encoding: [0x57,0x00,0x00,0x00]
#CHECK: x %r0, 4095 # encoding: [0x57,0x00,0x0f,0xff]
#CHECK: x %r0, 0(%r1) # encoding: [0x57,0x00,0x10,0x00]
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