[PATCH] D27317: AMDGPU: Fix handling of 16-bit immediates

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl.

Since 32-bit instructions with 32-bit input immediate behavior
are used to materialize 16-bit constants in 32-bit registers
for 16-bit instructions, determining the legality based
on the size is incorrect. Change operands to have the size
specified in the type.

      

Also adds a workaround for a disassembler bug that
produces an immediate MCOperand for an operand that
is supposed to be OPERAND_REGISTER.

      

The assembler appears to accept out of bounds immediates and
truncates them, but this seems to be an issue for 32-bit
already.


https://reviews.llvm.org/D27317

Files:
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
  lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  lib/Target/AMDGPU/SIDefines.h
  lib/Target/AMDGPU/SIFoldOperands.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SIRegisterInfo.td
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  lib/Target/AMDGPU/VOP2Instructions.td
  test/CodeGen/AMDGPU/commute-compares.ll
  test/CodeGen/AMDGPU/fadd.f16.ll
  test/CodeGen/AMDGPU/fmul.f16.ll
  test/CodeGen/AMDGPU/fsub.f16.ll
  test/CodeGen/AMDGPU/imm16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll
  test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
  test/CodeGen/AMDGPU/llvm.minnum.f16.ll
  test/CodeGen/AMDGPU/select.f16.ll
  test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
  test/MC/AMDGPU/literal16.s
  test/MC/AMDGPU/vop2.s
  test/MC/Disassembler/AMDGPU/literal16_vi.txt
  test/MC/Disassembler/AMDGPU/missing_op.txt
  test/MC/Disassembler/AMDGPU/vop1.txt

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