[PATCH] D25318: [DAG] Don't increase SDNodeOrder for dbg.value/declare.

[Adrian Prantl via Phabricator via llvm-commits]

aprantl added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:976
 
-  ++SDNodeOrder;
+  // Increase the SDNodeOrder if dealing with a non-debug instruction
+  if (!isa<DbgValueInst>(I) && !isa<DbgDeclareInst>(I))
----------------
and  a `.` at the end of the comment ;-)


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:977
+  // Increase the SDNodeOrder if dealing with a non-debug instruction
+  if (!isa<DbgValueInst>(I) && !isa<DbgDeclareInst>(I))
+    ++SDNodeOrder;
----------------
fhahn wrote:
> I think you could use  if (!isa<DbgInfoIntrinsic>(I)) here.
This would be not just shorter but also more future-proof.


================
Comment at: test/DebugInfo/Generic/selectiondag-order.ll:5
+; llvm.dbg.value in fn1_dbg. The generated instruction should be identical.
+; However currently we just check the first pushq.
+
----------------
Is there a good reason for this? Does it make the testcase more stable?
If we only check the first instruction, sh/could we simplify the IR?


https://reviews.llvm.org/D25318