[llvm] r288290 - MCStreamer: Use "cfi" for CFI related temp labels.
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 15:48:28 PST 2016
Author: matze
Date: Wed Nov 30 17:48:26 2016
New Revision: 288290
URL: http://llvm.org/viewvc/llvm-project?rev=288290&view=rev
Log:
MCStreamer: Use "cfi" for CFI related temp labels.
Choosing a "cfi" name makes the intend a bit clearer in an assembly dump
and more importantly the assembly dumps are slightly more stable as the
numbers don't move around anymore when unrelated code calls
createTempSymbol() more or less often.
As they are temp labels the name doesn't influence the generated object
code.
Differential Revision: https://reviews.llvm.org/D27244
Modified:
llvm/trunk/include/llvm/MC/MCStreamer.h
llvm/trunk/lib/MC/MCStreamer.cpp
llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
llvm/trunk/test/CodeGen/X86/avg.ll
llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll
llvm/trunk/test/CodeGen/X86/avx512-fsel.ll
llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
llvm/trunk/test/CodeGen/X86/avx512-mask-spills.ll
llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll
llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll
llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll
llvm/trunk/test/CodeGen/X86/fast-isel-store.ll
llvm/trunk/test/CodeGen/X86/haddsub-2.ll
llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll
llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll
llvm/trunk/test/CodeGen/X86/memset-nonzero.ll
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
llvm/trunk/test/CodeGen/X86/movpc32-check.ll
llvm/trunk/test/CodeGen/X86/patchpoint-webkit_jscc.ll
llvm/trunk/test/CodeGen/X86/pr27071.ll
llvm/trunk/test/CodeGen/X86/pr29112.ll
llvm/trunk/test/CodeGen/X86/pr30430.ll
llvm/trunk/test/CodeGen/X86/push-cfi.ll
llvm/trunk/test/CodeGen/X86/setcc-lowering.ll
llvm/trunk/test/CodeGen/X86/statepoint-allocas.ll
llvm/trunk/test/CodeGen/X86/statepoint-call-lowering.ll
llvm/trunk/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll
llvm/trunk/test/CodeGen/X86/statepoint-stackmap-format.ll
llvm/trunk/test/CodeGen/X86/statepoint-vector.ll
llvm/trunk/test/CodeGen/X86/tls-pie.ll
llvm/trunk/test/CodeGen/X86/tls-shrink-wrapping.ll
llvm/trunk/test/CodeGen/X86/vector-sext.ll
llvm/trunk/test/CodeGen/X86/vector-shuffle-mmx.ll
llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll
llvm/trunk/test/CodeGen/X86/win-cleanuppad.ll
llvm/trunk/test/CodeGen/X86/win32-pic-jumptable.ll
llvm/trunk/test/CodeGen/XCore/epilogue_prologue.ll
Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed Nov 30 17:48:26 2016
@@ -169,6 +169,7 @@ class MCStreamer {
MCDwarfFrameInfo *getCurrentDwarfFrameInfo();
void EnsureValidDwarfFrame();
+ MCSymbol *EmitCFILabel();
MCSymbol *EmitCFICommon();
std::vector<WinEH::FrameInfo *> WinFrameInfos;
Modified: llvm/trunk/lib/MC/MCStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCStreamer.cpp Wed Nov 30 17:48:26 2016
@@ -341,13 +341,17 @@ void MCStreamer::EmitCFIEndProcImpl(MCDw
Frame.End = (MCSymbol *) 1;
}
-MCSymbol *MCStreamer::EmitCFICommon() {
- EnsureValidDwarfFrame();
- MCSymbol *Label = getContext().createTempSymbol();
+MCSymbol *MCStreamer::EmitCFILabel() {
+ MCSymbol *Label = getContext().createTempSymbol("cfi", true);
EmitLabel(Label);
return Label;
}
+MCSymbol *MCStreamer::EmitCFICommon() {
+ EnsureValidDwarfFrame();
+ return EmitCFILabel();
+}
+
void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) {
MCSymbol *Label = EmitCFICommon();
MCCFIInstruction Instruction =
@@ -504,8 +508,7 @@ void MCStreamer::EmitWinCFIStartProc(con
if (CurrentWinFrameInfo && !CurrentWinFrameInfo->End)
report_fatal_error("Starting a function before ending the previous one!");
- MCSymbol *StartProc = getContext().createTempSymbol();
- EmitLabel(StartProc);
+ MCSymbol *StartProc = EmitCFILabel();
WinFrameInfos.push_back(new WinEH::FrameInfo(Symbol, StartProc));
CurrentWinFrameInfo = WinFrameInfos.back();
@@ -517,16 +520,14 @@ void MCStreamer::EmitWinCFIEndProc() {
if (CurrentWinFrameInfo->ChainedParent)
report_fatal_error("Not all chained regions terminated!");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
CurrentWinFrameInfo->End = Label;
}
void MCStreamer::EmitWinCFIStartChained() {
EnsureValidWinFrameInfo();
- MCSymbol *StartProc = getContext().createTempSymbol();
- EmitLabel(StartProc);
+ MCSymbol *StartProc = EmitCFILabel();
WinFrameInfos.push_back(new WinEH::FrameInfo(CurrentWinFrameInfo->Function,
StartProc, CurrentWinFrameInfo));
@@ -539,8 +540,7 @@ void MCStreamer::EmitWinCFIEndChained()
if (!CurrentWinFrameInfo->ChainedParent)
report_fatal_error("End of a chained region outside a chained region!");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
CurrentWinFrameInfo->End = Label;
CurrentWinFrameInfo =
@@ -604,8 +604,7 @@ void MCStreamer::EmitSyntaxDirective() {
void MCStreamer::EmitWinCFIPushReg(unsigned Register) {
EnsureValidWinFrameInfo();
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
WinEH::Instruction Inst = Win64EH::Instruction::PushNonVol(Label, Register);
CurrentWinFrameInfo->Instructions.push_back(Inst);
@@ -620,8 +619,7 @@ void MCStreamer::EmitWinCFISetFrame(unsi
if (Offset > 240)
report_fatal_error("Frame offset must be less than or equal to 240!");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
WinEH::Instruction Inst =
Win64EH::Instruction::SetFPReg(Label, Register, Offset);
@@ -636,8 +634,7 @@ void MCStreamer::EmitWinCFIAllocStack(un
if (Size & 7)
report_fatal_error("Misaligned stack allocation!");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
WinEH::Instruction Inst = Win64EH::Instruction::Alloc(Label, Size);
CurrentWinFrameInfo->Instructions.push_back(Inst);
@@ -648,8 +645,7 @@ void MCStreamer::EmitWinCFISaveReg(unsig
if (Offset & 7)
report_fatal_error("Misaligned saved register offset!");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
WinEH::Instruction Inst =
Win64EH::Instruction::SaveNonVol(Label, Register, Offset);
@@ -661,8 +657,7 @@ void MCStreamer::EmitWinCFISaveXMM(unsig
if (Offset & 0x0F)
report_fatal_error("Misaligned saved vector register offset!");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
WinEH::Instruction Inst =
Win64EH::Instruction::SaveXMM(Label, Register, Offset);
@@ -674,8 +669,7 @@ void MCStreamer::EmitWinCFIPushFrame(boo
if (CurrentWinFrameInfo->Instructions.size() > 0)
report_fatal_error("If present, PushMachFrame must be the first UOP");
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
WinEH::Instruction Inst = Win64EH::Instruction::PushMachFrame(Label, Code);
CurrentWinFrameInfo->Instructions.push_back(Inst);
@@ -684,8 +678,7 @@ void MCStreamer::EmitWinCFIPushFrame(boo
void MCStreamer::EmitWinCFIEndProlog() {
EnsureValidWinFrameInfo();
- MCSymbol *Label = getContext().createTempSymbol();
- EmitLabel(Label);
+ MCSymbol *Label = EmitCFILabel();
CurrentWinFrameInfo->PrologEnd = Label;
}
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll Wed Nov 30 17:48:26 2016
@@ -13,7 +13,7 @@
define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen:
-; CHECK: Ltmp
+; CHECK: Lcfi
; CHECK: str x{{.+}}, [sp]
; CHECK-NEXT: mov x0, x{{.+}}
; CHECK: Ltmp
@@ -22,7 +22,7 @@ entry:
; CHECK: movk x16, #48879
; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen:
-; FAST: Ltmp
+; FAST: Lcfi
; FAST: str x{{.+}}, [sp]
; FAST: Ltmp
; FAST-NEXT: mov x16, #281470681743360
@@ -40,7 +40,7 @@ entry:
define i64 @jscall_patchpoint_codegen2(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK: Ltmp
+; CHECK: Lcfi
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK-NEXT: str x[[REG]], [sp, #24]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
@@ -53,7 +53,7 @@ entry:
; CHECK-NEXT: movk x16, #48879
; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen2:
-; FAST: Ltmp
+; FAST: Lcfi
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
@@ -74,7 +74,7 @@ entry:
define i64 @jscall_patchpoint_codegen3(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen3:
-; CHECK: Ltmp
+; CHECK: Lcfi
; CHECK: mov w[[REG:[0-9]+]], #10
; CHECK-NEXT: str x[[REG]], [sp, #48]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
@@ -91,7 +91,7 @@ entry:
; CHECK-NEXT: movk x16, #48879
; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen3:
-; FAST: Ltmp
+; FAST: Lcfi
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
Modified: llvm/trunk/test/CodeGen/X86/avg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avg.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avg.ll Wed Nov 30 17:48:26 2016
@@ -258,7 +258,7 @@ define void @avg_v64i8(<64 x i8>* %a, <6
; SSE2-LABEL: avg_v64i8:
; SSE2: # BB#0:
; SSE2-NEXT: subq $152, %rsp
-; SSE2-NEXT: .Ltmp0:
+; SSE2-NEXT: .Lcfi0:
; SSE2-NEXT: .cfi_def_cfa_offset 160
; SSE2-NEXT: movdqa (%rdi), %xmm1
; SSE2-NEXT: movdqa 16(%rdi), %xmm2
Modified: llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll Wed Nov 30 17:48:26 2016
@@ -1108,7 +1108,7 @@ define void @isel_crash_16b(i8* %cV_R.ad
; X32-AVX2-LABEL: isel_crash_16b:
; X32-AVX2: ## BB#0: ## %eintry
; X32-AVX2-NEXT: subl $60, %esp
-; X32-AVX2-NEXT: Ltmp0:
+; X32-AVX2-NEXT: Lcfi0:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 64
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1133,7 +1133,7 @@ define void @isel_crash_16b(i8* %cV_R.ad
; X32-AVX512VL-LABEL: isel_crash_16b:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: subl $60, %esp
-; X32-AVX512VL-NEXT: Ltmp0:
+; X32-AVX512VL-NEXT: Lcfi0:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 64
; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1173,12 +1173,12 @@ define void @isel_crash_32b(i8* %cV_R.ad
; X32-AVX2-LABEL: isel_crash_32b:
; X32-AVX2: ## BB#0: ## %eintry
; X32-AVX2-NEXT: pushl %ebp
-; X32-AVX2-NEXT: Ltmp1:
+; X32-AVX2-NEXT: Lcfi1:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT: Ltmp2:
+; X32-AVX2-NEXT: Lcfi2:
; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-AVX2-NEXT: movl %esp, %ebp
-; X32-AVX2-NEXT: Ltmp3:
+; X32-AVX2-NEXT: Lcfi3:
; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX2-NEXT: andl $-32, %esp
; X32-AVX2-NEXT: subl $128, %esp
@@ -1196,12 +1196,12 @@ define void @isel_crash_32b(i8* %cV_R.ad
; X64-AVX2-LABEL: isel_crash_32b:
; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp
-; X64-AVX2-NEXT: Ltmp0:
+; X64-AVX2-NEXT: Lcfi0:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT: Ltmp1:
+; X64-AVX2-NEXT: Lcfi1:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp
-; X64-AVX2-NEXT: Ltmp2:
+; X64-AVX2-NEXT: Lcfi2:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp
@@ -1220,12 +1220,12 @@ define void @isel_crash_32b(i8* %cV_R.ad
; X32-AVX512VL-LABEL: isel_crash_32b:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
-; X32-AVX512VL-NEXT: Ltmp1:
+; X32-AVX512VL-NEXT: Lcfi1:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT: Ltmp2:
+; X32-AVX512VL-NEXT: Lcfi2:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
-; X32-AVX512VL-NEXT: Ltmp3:
+; X32-AVX512VL-NEXT: Lcfi3:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
@@ -1242,12 +1242,12 @@ define void @isel_crash_32b(i8* %cV_R.ad
; X64-AVX512VL-LABEL: isel_crash_32b:
; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp
-; X64-AVX512VL-NEXT: Ltmp0:
+; X64-AVX512VL-NEXT: Lcfi0:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT: Ltmp1:
+; X64-AVX512VL-NEXT: Lcfi1:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp
-; X64-AVX512VL-NEXT: Ltmp2:
+; X64-AVX512VL-NEXT: Lcfi2:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp
@@ -1280,7 +1280,7 @@ define void @isel_crash_8w(i16* %cV_R.ad
; X32-AVX2-LABEL: isel_crash_8w:
; X32-AVX2: ## BB#0: ## %entry
; X32-AVX2-NEXT: subl $60, %esp
-; X32-AVX2-NEXT: Ltmp4:
+; X32-AVX2-NEXT: Lcfi4:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 64
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1305,7 +1305,7 @@ define void @isel_crash_8w(i16* %cV_R.ad
; X32-AVX512VL-LABEL: isel_crash_8w:
; X32-AVX512VL: ## BB#0: ## %entry
; X32-AVX512VL-NEXT: subl $60, %esp
-; X32-AVX512VL-NEXT: Ltmp4:
+; X32-AVX512VL-NEXT: Lcfi4:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 64
; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1345,12 +1345,12 @@ define void @isel_crash_16w(i16* %cV_R.a
; X32-AVX2-LABEL: isel_crash_16w:
; X32-AVX2: ## BB#0: ## %eintry
; X32-AVX2-NEXT: pushl %ebp
-; X32-AVX2-NEXT: Ltmp5:
+; X32-AVX2-NEXT: Lcfi5:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT: Ltmp6:
+; X32-AVX2-NEXT: Lcfi6:
; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-AVX2-NEXT: movl %esp, %ebp
-; X32-AVX2-NEXT: Ltmp7:
+; X32-AVX2-NEXT: Lcfi7:
; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX2-NEXT: andl $-32, %esp
; X32-AVX2-NEXT: subl $128, %esp
@@ -1368,12 +1368,12 @@ define void @isel_crash_16w(i16* %cV_R.a
; X64-AVX2-LABEL: isel_crash_16w:
; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp
-; X64-AVX2-NEXT: Ltmp3:
+; X64-AVX2-NEXT: Lcfi3:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT: Ltmp4:
+; X64-AVX2-NEXT: Lcfi4:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp
-; X64-AVX2-NEXT: Ltmp5:
+; X64-AVX2-NEXT: Lcfi5:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp
@@ -1392,12 +1392,12 @@ define void @isel_crash_16w(i16* %cV_R.a
; X32-AVX512VL-LABEL: isel_crash_16w:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
-; X32-AVX512VL-NEXT: Ltmp5:
+; X32-AVX512VL-NEXT: Lcfi5:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT: Ltmp6:
+; X32-AVX512VL-NEXT: Lcfi6:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
-; X32-AVX512VL-NEXT: Ltmp7:
+; X32-AVX512VL-NEXT: Lcfi7:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
@@ -1414,12 +1414,12 @@ define void @isel_crash_16w(i16* %cV_R.a
; X64-AVX512VL-LABEL: isel_crash_16w:
; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp
-; X64-AVX512VL-NEXT: Ltmp3:
+; X64-AVX512VL-NEXT: Lcfi3:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT: Ltmp4:
+; X64-AVX512VL-NEXT: Lcfi4:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp
-; X64-AVX512VL-NEXT: Ltmp5:
+; X64-AVX512VL-NEXT: Lcfi5:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp
@@ -1452,7 +1452,7 @@ define void @isel_crash_4d(i32* %cV_R.ad
; X32-LABEL: isel_crash_4d:
; X32: ## BB#0: ## %entry
; X32-NEXT: subl $60, %esp
-; X32-NEXT: Ltmp8:
+; X32-NEXT: Lcfi8:
; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1502,12 +1502,12 @@ define void @isel_crash_8d(i32* %cV_R.ad
; X32-AVX2-LABEL: isel_crash_8d:
; X32-AVX2: ## BB#0: ## %eintry
; X32-AVX2-NEXT: pushl %ebp
-; X32-AVX2-NEXT: Ltmp9:
+; X32-AVX2-NEXT: Lcfi9:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT: Ltmp10:
+; X32-AVX2-NEXT: Lcfi10:
; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-AVX2-NEXT: movl %esp, %ebp
-; X32-AVX2-NEXT: Ltmp11:
+; X32-AVX2-NEXT: Lcfi11:
; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX2-NEXT: andl $-32, %esp
; X32-AVX2-NEXT: subl $128, %esp
@@ -1525,12 +1525,12 @@ define void @isel_crash_8d(i32* %cV_R.ad
; X64-AVX2-LABEL: isel_crash_8d:
; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp
-; X64-AVX2-NEXT: Ltmp6:
+; X64-AVX2-NEXT: Lcfi6:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT: Ltmp7:
+; X64-AVX2-NEXT: Lcfi7:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp
-; X64-AVX2-NEXT: Ltmp8:
+; X64-AVX2-NEXT: Lcfi8:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp
@@ -1549,12 +1549,12 @@ define void @isel_crash_8d(i32* %cV_R.ad
; X32-AVX512VL-LABEL: isel_crash_8d:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
-; X32-AVX512VL-NEXT: Ltmp9:
+; X32-AVX512VL-NEXT: Lcfi9:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT: Ltmp10:
+; X32-AVX512VL-NEXT: Lcfi10:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
-; X32-AVX512VL-NEXT: Ltmp11:
+; X32-AVX512VL-NEXT: Lcfi11:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
@@ -1571,12 +1571,12 @@ define void @isel_crash_8d(i32* %cV_R.ad
; X64-AVX512VL-LABEL: isel_crash_8d:
; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp
-; X64-AVX512VL-NEXT: Ltmp6:
+; X64-AVX512VL-NEXT: Lcfi6:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT: Ltmp7:
+; X64-AVX512VL-NEXT: Lcfi7:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp
-; X64-AVX512VL-NEXT: Ltmp8:
+; X64-AVX512VL-NEXT: Lcfi8:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp
@@ -1608,7 +1608,7 @@ define void @isel_crash_2q(i64* %cV_R.ad
; X32-AVX2-LABEL: isel_crash_2q:
; X32-AVX2: ## BB#0: ## %entry
; X32-AVX2-NEXT: subl $60, %esp
-; X32-AVX2-NEXT: Ltmp12:
+; X32-AVX2-NEXT: Lcfi12:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 64
; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1638,7 +1638,7 @@ define void @isel_crash_2q(i64* %cV_R.ad
; X32-AVX512VL-LABEL: isel_crash_2q:
; X32-AVX512VL: ## BB#0: ## %entry
; X32-AVX512VL-NEXT: subl $60, %esp
-; X32-AVX512VL-NEXT: Ltmp12:
+; X32-AVX512VL-NEXT: Lcfi12:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 64
; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0
@@ -1681,12 +1681,12 @@ define void @isel_crash_4q(i64* %cV_R.ad
; X32-AVX2-LABEL: isel_crash_4q:
; X32-AVX2: ## BB#0: ## %eintry
; X32-AVX2-NEXT: pushl %ebp
-; X32-AVX2-NEXT: Ltmp13:
+; X32-AVX2-NEXT: Lcfi13:
; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX2-NEXT: Ltmp14:
+; X32-AVX2-NEXT: Lcfi14:
; X32-AVX2-NEXT: .cfi_offset %ebp, -8
; X32-AVX2-NEXT: movl %esp, %ebp
-; X32-AVX2-NEXT: Ltmp15:
+; X32-AVX2-NEXT: Lcfi15:
; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX2-NEXT: andl $-32, %esp
; X32-AVX2-NEXT: subl $128, %esp
@@ -1710,12 +1710,12 @@ define void @isel_crash_4q(i64* %cV_R.ad
; X64-AVX2-LABEL: isel_crash_4q:
; X64-AVX2: ## BB#0: ## %eintry
; X64-AVX2-NEXT: pushq %rbp
-; X64-AVX2-NEXT: Ltmp9:
+; X64-AVX2-NEXT: Lcfi9:
; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX2-NEXT: Ltmp10:
+; X64-AVX2-NEXT: Lcfi10:
; X64-AVX2-NEXT: .cfi_offset %rbp, -16
; X64-AVX2-NEXT: movq %rsp, %rbp
-; X64-AVX2-NEXT: Ltmp11:
+; X64-AVX2-NEXT: Lcfi11:
; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX2-NEXT: andq $-32, %rsp
; X64-AVX2-NEXT: subq $128, %rsp
@@ -1734,12 +1734,12 @@ define void @isel_crash_4q(i64* %cV_R.ad
; X32-AVX512VL-LABEL: isel_crash_4q:
; X32-AVX512VL: ## BB#0: ## %eintry
; X32-AVX512VL-NEXT: pushl %ebp
-; X32-AVX512VL-NEXT: Ltmp13:
+; X32-AVX512VL-NEXT: Lcfi13:
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
-; X32-AVX512VL-NEXT: Ltmp14:
+; X32-AVX512VL-NEXT: Lcfi14:
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
; X32-AVX512VL-NEXT: movl %esp, %ebp
-; X32-AVX512VL-NEXT: Ltmp15:
+; X32-AVX512VL-NEXT: Lcfi15:
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
; X32-AVX512VL-NEXT: andl $-32, %esp
; X32-AVX512VL-NEXT: subl $128, %esp
@@ -1762,12 +1762,12 @@ define void @isel_crash_4q(i64* %cV_R.ad
; X64-AVX512VL-LABEL: isel_crash_4q:
; X64-AVX512VL: ## BB#0: ## %eintry
; X64-AVX512VL-NEXT: pushq %rbp
-; X64-AVX512VL-NEXT: Ltmp9:
+; X64-AVX512VL-NEXT: Lcfi9:
; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
-; X64-AVX512VL-NEXT: Ltmp10:
+; X64-AVX512VL-NEXT: Lcfi10:
; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
; X64-AVX512VL-NEXT: movq %rsp, %rbp
-; X64-AVX512VL-NEXT: Ltmp11:
+; X64-AVX512VL-NEXT: Lcfi11:
; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
; X64-AVX512VL-NEXT: andq $-32, %rsp
; X64-AVX512VL-NEXT: subq $128, %rsp
Modified: llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-calling-conv.ll Wed Nov 30 17:48:26 2016
@@ -125,7 +125,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8
; KNL-LABEL: test5:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rax
-; KNL-NEXT: Ltmp0:
+; KNL-NEXT: Lcfi0:
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
@@ -140,7 +140,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8
; SKX-LABEL: test5:
; SKX: ## BB#0:
; SKX-NEXT: pushq %rax
-; SKX-NEXT: Ltmp0:
+; SKX-NEXT: Lcfi0:
; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %xmm0
@@ -154,7 +154,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8
; KNL_X32-LABEL: test5:
; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp
-; KNL_X32-NEXT: Ltmp0:
+; KNL_X32-NEXT: Lcfi0:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
@@ -177,7 +177,7 @@ define <16 x i32> @test6(<16 x i32>%a, <
; KNL-LABEL: test6:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rax
-; KNL-NEXT: Ltmp1:
+; KNL-NEXT: Lcfi1:
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
@@ -193,7 +193,7 @@ define <16 x i32> @test6(<16 x i32>%a, <
; SKX-LABEL: test6:
; SKX: ## BB#0:
; SKX-NEXT: pushq %rax
-; SKX-NEXT: Ltmp1:
+; SKX-NEXT: Lcfi1:
; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %xmm0
@@ -207,7 +207,7 @@ define <16 x i32> @test6(<16 x i32>%a, <
; KNL_X32-LABEL: test6:
; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp
-; KNL_X32-NEXT: Ltmp1:
+; KNL_X32-NEXT: Lcfi1:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %zmm1, %zmm0, %k1
; KNL_X32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0
@@ -231,7 +231,7 @@ define <4 x i32> @test7(<4 x i32>%a, <4
; KNL-LABEL: test7:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rax
-; KNL-NEXT: Ltmp2:
+; KNL-NEXT: Lcfi2:
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; KNL-NEXT: callq _func4xi1
@@ -243,7 +243,7 @@ define <4 x i32> @test7(<4 x i32>%a, <4
; SKX-LABEL: test7:
; SKX: ## BB#0:
; SKX-NEXT: pushq %rax
-; SKX-NEXT: Ltmp2:
+; SKX-NEXT: Lcfi2:
; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %xmm0
@@ -256,7 +256,7 @@ define <4 x i32> @test7(<4 x i32>%a, <4
; KNL_X32-LABEL: test7:
; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp
-; KNL_X32-NEXT: Ltmp2:
+; KNL_X32-NEXT: Lcfi2:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; KNL_X32-NEXT: calll _func4xi1
@@ -274,7 +274,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8
; KNL-LABEL: test7a:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rax
-; KNL-NEXT: Ltmp3:
+; KNL-NEXT: Lcfi3:
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
@@ -294,7 +294,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8
; SKX-LABEL: test7a:
; SKX: ## BB#0:
; SKX-NEXT: pushq %rax
-; SKX-NEXT: Ltmp3:
+; SKX-NEXT: Lcfi3:
; SKX-NEXT: .cfi_def_cfa_offset 16
; SKX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0
; SKX-NEXT: vpmovm2w %k0, %xmm0
@@ -311,7 +311,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8
; KNL_X32-LABEL: test7a:
; KNL_X32: ## BB#0:
; KNL_X32-NEXT: subl $12, %esp
-; KNL_X32-NEXT: Ltmp3:
+; KNL_X32-NEXT: Lcfi3:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
@@ -413,19 +413,19 @@ define i32 @test12(i32 %a1, i32 %a2, i32
; ALL_X64-LABEL: test12:
; ALL_X64: ## BB#0:
; ALL_X64-NEXT: pushq %rbp
-; ALL_X64-NEXT: Ltmp4:
+; ALL_X64-NEXT: Lcfi4:
; ALL_X64-NEXT: .cfi_def_cfa_offset 16
; ALL_X64-NEXT: pushq %r14
-; ALL_X64-NEXT: Ltmp5:
+; ALL_X64-NEXT: Lcfi5:
; ALL_X64-NEXT: .cfi_def_cfa_offset 24
; ALL_X64-NEXT: pushq %rbx
-; ALL_X64-NEXT: Ltmp6:
+; ALL_X64-NEXT: Lcfi6:
; ALL_X64-NEXT: .cfi_def_cfa_offset 32
-; ALL_X64-NEXT: Ltmp7:
+; ALL_X64-NEXT: Lcfi7:
; ALL_X64-NEXT: .cfi_offset %rbx, -32
-; ALL_X64-NEXT: Ltmp8:
+; ALL_X64-NEXT: Lcfi8:
; ALL_X64-NEXT: .cfi_offset %r14, -24
-; ALL_X64-NEXT: Ltmp9:
+; ALL_X64-NEXT: Lcfi9:
; ALL_X64-NEXT: .cfi_offset %rbp, -16
; ALL_X64-NEXT: movl %esi, %r14d
; ALL_X64-NEXT: movl %edi, %ebp
@@ -447,22 +447,22 @@ define i32 @test12(i32 %a1, i32 %a2, i32
; KNL_X32-LABEL: test12:
; KNL_X32: ## BB#0:
; KNL_X32-NEXT: pushl %ebx
-; KNL_X32-NEXT: Ltmp4:
+; KNL_X32-NEXT: Lcfi4:
; KNL_X32-NEXT: .cfi_def_cfa_offset 8
; KNL_X32-NEXT: pushl %edi
-; KNL_X32-NEXT: Ltmp5:
+; KNL_X32-NEXT: Lcfi5:
; KNL_X32-NEXT: .cfi_def_cfa_offset 12
; KNL_X32-NEXT: pushl %esi
-; KNL_X32-NEXT: Ltmp6:
+; KNL_X32-NEXT: Lcfi6:
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: subl $16, %esp
-; KNL_X32-NEXT: Ltmp7:
+; KNL_X32-NEXT: Lcfi7:
; KNL_X32-NEXT: .cfi_def_cfa_offset 32
-; KNL_X32-NEXT: Ltmp8:
+; KNL_X32-NEXT: Lcfi8:
; KNL_X32-NEXT: .cfi_offset %esi, -16
-; KNL_X32-NEXT: Ltmp9:
+; KNL_X32-NEXT: Lcfi9:
; KNL_X32-NEXT: .cfi_offset %edi, -12
-; KNL_X32-NEXT: Ltmp10:
+; KNL_X32-NEXT: Lcfi10:
; KNL_X32-NEXT: .cfi_offset %ebx, -8
; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; KNL_X32-NEXT: movl {{[0-9]+}}(%esp), %edi
Modified: llvm/trunk/test/CodeGen/X86/avx512-fsel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-fsel.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-fsel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-fsel.ll Wed Nov 30 17:48:26 2016
@@ -8,7 +8,7 @@ define i32 @test(float %a, float %b) {
; CHECK-LABEL: test:
; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: Ltmp0:
+; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: vucomiss %xmm1, %xmm0
Modified: llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll Wed Nov 30 17:48:26 2016
@@ -1044,12 +1044,12 @@ define i32 @test_insertelement_v32i1(i32
; KNL-LABEL: test_insertelement_v32i1:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp
-; KNL-NEXT: Ltmp0:
+; KNL-NEXT: Lcfi0:
; KNL-NEXT: .cfi_def_cfa_offset 16
-; KNL-NEXT: Ltmp1:
+; KNL-NEXT: Lcfi1:
; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp
-; KNL-NEXT: Ltmp2:
+; KNL-NEXT: Lcfi2:
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $32, %rsp
Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll Wed Nov 30 17:48:26 2016
@@ -498,12 +498,12 @@ define <64 x i8> @test16(i64 %x) {
; KNL-LABEL: test16:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp
-; KNL-NEXT: Ltmp0:
+; KNL-NEXT: Lcfi0:
; KNL-NEXT: .cfi_def_cfa_offset 16
-; KNL-NEXT: Ltmp1:
+; KNL-NEXT: Lcfi1:
; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp
-; KNL-NEXT: Ltmp2:
+; KNL-NEXT: Lcfi2:
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp
@@ -562,12 +562,12 @@ define <64 x i8> @test17(i64 %x, i32 %y,
; KNL-LABEL: test17:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp
-; KNL-NEXT: Ltmp3:
+; KNL-NEXT: Lcfi3:
; KNL-NEXT: .cfi_def_cfa_offset 16
-; KNL-NEXT: Ltmp4:
+; KNL-NEXT: Lcfi4:
; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp
-; KNL-NEXT: Ltmp5:
+; KNL-NEXT: Lcfi5:
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $64, %rsp
@@ -1033,12 +1033,12 @@ define void @ktest_2(<32 x float> %in, f
; KNL-LABEL: ktest_2:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp
-; KNL-NEXT: Ltmp6:
+; KNL-NEXT: Lcfi6:
; KNL-NEXT: .cfi_def_cfa_offset 16
-; KNL-NEXT: Ltmp7:
+; KNL-NEXT: Lcfi7:
; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: movq %rsp, %rbp
-; KNL-NEXT: Ltmp8:
+; KNL-NEXT: Lcfi8:
; KNL-NEXT: .cfi_def_cfa_register %rbp
; KNL-NEXT: andq $-32, %rsp
; KNL-NEXT: subq $32, %rsp
@@ -1630,34 +1630,34 @@ define void @store_64i1(<64 x i1>* %a, <
; KNL-LABEL: store_64i1:
; KNL: ## BB#0:
; KNL-NEXT: pushq %rbp
-; KNL-NEXT: Ltmp9:
+; KNL-NEXT: Lcfi9:
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: pushq %r15
-; KNL-NEXT: Ltmp10:
+; KNL-NEXT: Lcfi10:
; KNL-NEXT: .cfi_def_cfa_offset 24
; KNL-NEXT: pushq %r14
-; KNL-NEXT: Ltmp11:
+; KNL-NEXT: Lcfi11:
; KNL-NEXT: .cfi_def_cfa_offset 32
; KNL-NEXT: pushq %r13
-; KNL-NEXT: Ltmp12:
+; KNL-NEXT: Lcfi12:
; KNL-NEXT: .cfi_def_cfa_offset 40
; KNL-NEXT: pushq %r12
-; KNL-NEXT: Ltmp13:
+; KNL-NEXT: Lcfi13:
; KNL-NEXT: .cfi_def_cfa_offset 48
; KNL-NEXT: pushq %rbx
-; KNL-NEXT: Ltmp14:
+; KNL-NEXT: Lcfi14:
; KNL-NEXT: .cfi_def_cfa_offset 56
-; KNL-NEXT: Ltmp15:
+; KNL-NEXT: Lcfi15:
; KNL-NEXT: .cfi_offset %rbx, -56
-; KNL-NEXT: Ltmp16:
+; KNL-NEXT: Lcfi16:
; KNL-NEXT: .cfi_offset %r12, -48
-; KNL-NEXT: Ltmp17:
+; KNL-NEXT: Lcfi17:
; KNL-NEXT: .cfi_offset %r13, -40
-; KNL-NEXT: Ltmp18:
+; KNL-NEXT: Lcfi18:
; KNL-NEXT: .cfi_offset %r14, -32
-; KNL-NEXT: Ltmp19:
+; KNL-NEXT: Lcfi19:
; KNL-NEXT: .cfi_offset %r15, -24
-; KNL-NEXT: Ltmp20:
+; KNL-NEXT: Lcfi20:
; KNL-NEXT: .cfi_offset %rbp, -16
; KNL-NEXT: vpmovsxbd %xmm0, %zmm0
; KNL-NEXT: vpslld $31, %zmm0, %zmm0
Modified: llvm/trunk/test/CodeGen/X86/avx512-mask-spills.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-spills.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-mask-spills.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-mask-spills.ll Wed Nov 30 17:48:26 2016
@@ -6,7 +6,7 @@ define <4 x i1> @test_4i1(<4 x i32> %a,
; CHECK-LABEL: test_4i1:
; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: Ltmp0:
+; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleud %xmm1, %xmm0, %k0
; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
@@ -31,7 +31,7 @@ define <8 x i1> @test_8i1(<8 x i32> %a,
; CHECK-LABEL: test_8i1:
; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: Ltmp1:
+; CHECK-NEXT: Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleud %ymm1, %ymm0, %k0
; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
@@ -56,7 +56,7 @@ define <16 x i1> @test_16i1(<16 x i32> %
; CHECK-LABEL: test_16i1:
; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: Ltmp2:
+; CHECK-NEXT: Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleud %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Spill
@@ -80,7 +80,7 @@ define <32 x i1> @test_32i1(<32 x i16> %
; CHECK-LABEL: test_32i1:
; CHECK: ## BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: Ltmp3:
+; CHECK-NEXT: Lcfi3:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vpcmpnleuw %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovd %k0, {{[0-9]+}}(%rsp) ## 4-byte Spill
@@ -104,7 +104,7 @@ define <64 x i1> @test_64i1(<64 x i8> %a
; CHECK-LABEL: test_64i1:
; CHECK: ## BB#0:
; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: Ltmp4:
+; CHECK-NEXT: Lcfi4:
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: vpcmpnleub %zmm1, %zmm0, %k0
; CHECK-NEXT: kmovq %k0, {{[0-9]+}}(%rsp) ## 8-byte Spill
Modified: llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll Wed Nov 30 17:48:26 2016
@@ -408,7 +408,7 @@ define <16 x float> @broadcast_ss_spill(
; ALL-LABEL: broadcast_ss_spill:
; ALL: # BB#0:
; ALL-NEXT: pushq %rax
-; ALL-NEXT: .Ltmp0:
+; ALL-NEXT: .Lcfi0:
; ALL-NEXT: .cfi_def_cfa_offset 16
; ALL-NEXT: vaddss %xmm0, %xmm0, %xmm0
; ALL-NEXT: vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
@@ -428,7 +428,7 @@ define <8 x double> @broadcast_sd_spill(
; ALL-LABEL: broadcast_sd_spill:
; ALL: # BB#0:
; ALL-NEXT: pushq %rax
-; ALL-NEXT: .Ltmp1:
+; ALL-NEXT: .Lcfi1:
; ALL-NEXT: .cfi_def_cfa_offset 16
; ALL-NEXT: vaddsd %xmm0, %xmm0, %xmm0
; ALL-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll Wed Nov 30 17:48:26 2016
@@ -282,7 +282,7 @@ define i64 @test_pcmpeq_b(<64 x i8> %a,
; AVX512F-32-LABEL: test_pcmpeq_b:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp
-; AVX512F-32-NEXT: .Ltmp0:
+; AVX512F-32-NEXT: .Lcfi0:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp)
@@ -305,7 +305,7 @@ define i64 @test_mask_pcmpeq_b(<64 x i8>
; AVX512F-32-LABEL: test_mask_pcmpeq_b:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp
-; AVX512F-32-NEXT: .Ltmp1:
+; AVX512F-32-NEXT: .Lcfi1:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
@@ -366,7 +366,7 @@ define i64 @test_pcmpgt_b(<64 x i8> %a,
; AVX512F-32-LABEL: test_pcmpgt_b:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp
-; AVX512F-32-NEXT: .Ltmp2:
+; AVX512F-32-NEXT: .Lcfi2:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: vpcmpgtb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp)
@@ -389,7 +389,7 @@ define i64 @test_mask_pcmpgt_b(<64 x i8>
; AVX512F-32-LABEL: test_mask_pcmpgt_b:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp
-; AVX512F-32-NEXT: .Ltmp3:
+; AVX512F-32-NEXT: .Lcfi3:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: kmovq {{[0-9]+}}(%esp), %k1
; AVX512F-32-NEXT: vpcmpgtb %zmm1, %zmm0, %k0 {%k1}
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Wed Nov 30 17:48:26 2016
@@ -33,7 +33,7 @@ define i64 @test_cmp_b_512(<64 x i8> %a0
; AVX512F-32-LABEL: test_cmp_b_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $68, %esp
-; AVX512F-32-NEXT: .Ltmp0:
+; AVX512F-32-NEXT: .Lcfi0:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: vpcmpeqb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
@@ -119,7 +119,7 @@ define i64 @test_mask_cmp_b_512(<64 x i8
; AVX512F-32-LABEL: test_mask_cmp_b_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $68, %esp
-; AVX512F-32-NEXT: .Ltmp1:
+; AVX512F-32-NEXT: .Lcfi1:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
@@ -209,7 +209,7 @@ define i64 @test_ucmp_b_512(<64 x i8> %a
; AVX512F-32-LABEL: test_ucmp_b_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $68, %esp
-; AVX512F-32-NEXT: .Ltmp2:
+; AVX512F-32-NEXT: .Lcfi2:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: vpcmpequb %zmm1, %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, {{[0-9]+}}(%esp)
@@ -295,7 +295,7 @@ define i64 @test_mask_x86_avx512_ucmp_b_
; AVX512F-32-LABEL: test_mask_x86_avx512_ucmp_b_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $68, %esp
-; AVX512F-32-NEXT: .Ltmp3:
+; AVX512F-32-NEXT: .Lcfi3:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 72
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
@@ -2189,7 +2189,7 @@ define i64 at test_int_x86_avx512_kunpck_qd
; AVX512F-32-LABEL: test_int_x86_avx512_kunpck_qd:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp
-; AVX512F-32-NEXT: .Ltmp4:
+; AVX512F-32-NEXT: .Lcfi4:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
@@ -2215,7 +2215,7 @@ define i64 at test_int_x86_avx512_cvtb2mask
; AVX512F-32-LABEL: test_int_x86_avx512_cvtb2mask_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $12, %esp
-; AVX512F-32-NEXT: .Ltmp5:
+; AVX512F-32-NEXT: .Lcfi5:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 16
; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0
; AVX512F-32-NEXT: kmovq %k0, (%esp)
@@ -2437,7 +2437,7 @@ define i64 at test_int_x86_avx512_ptestm_b_
; AVX512F-32-LABEL: test_int_x86_avx512_ptestm_b_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $20, %esp
-; AVX512F-32-NEXT: .Ltmp6:
+; AVX512F-32-NEXT: .Lcfi6:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 24
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
@@ -2502,7 +2502,7 @@ define i64 at test_int_x86_avx512_ptestnm_b
; AVX512F-32-LABEL: test_int_x86_avx512_ptestnm_b_512:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: subl $20, %esp
-; AVX512F-32-NEXT: .Ltmp7:
+; AVX512F-32-NEXT: .Lcfi7:
; AVX512F-32-NEXT: .cfi_def_cfa_offset 24
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0
; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll Wed Nov 30 17:48:26 2016
@@ -24,7 +24,7 @@ define <2 x i64> @test_mm_mask_broadcast
; X32-LABEL: test_mm_mask_broadcastd_epi32:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp0:
+; X32-NEXT: .Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -57,7 +57,7 @@ define <2 x i64> @test_mm_maskz_broadcas
; X32-LABEL: test_mm_maskz_broadcastd_epi32:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp1:
+; X32-NEXT: .Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -162,7 +162,7 @@ define <2 x i64> @test_mm_mask_broadcast
; X32-LABEL: test_mm_mask_broadcastq_epi64:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp2:
+; X32-NEXT: .Lcfi2:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -192,7 +192,7 @@ define <2 x i64> @test_mm_maskz_broadcas
; X32-LABEL: test_mm_maskz_broadcastq_epi64:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp3:
+; X32-NEXT: .Lcfi3:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -236,7 +236,7 @@ define <4 x i64> @test_mm256_mask_broadc
; X32-LABEL: test_mm256_mask_broadcastq_epi64:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp4:
+; X32-NEXT: .Lcfi4:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -266,7 +266,7 @@ define <4 x i64> @test_mm256_maskz_broad
; X32-LABEL: test_mm256_maskz_broadcastq_epi64:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp5:
+; X32-NEXT: .Lcfi5:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -310,7 +310,7 @@ define <2 x double> @test_mm_mask_broadc
; X32-LABEL: test_mm_mask_broadcastsd_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp6:
+; X32-NEXT: .Lcfi6:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -340,7 +340,7 @@ define <2 x double> @test_mm_maskz_broad
; X32-LABEL: test_mm_maskz_broadcastsd_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp7:
+; X32-NEXT: .Lcfi7:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -384,7 +384,7 @@ define <4 x double> @test_mm256_mask_bro
; X32-LABEL: test_mm256_mask_broadcastsd_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp8:
+; X32-NEXT: .Lcfi8:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -414,7 +414,7 @@ define <4 x double> @test_mm256_maskz_br
; X32-LABEL: test_mm256_maskz_broadcastsd_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp9:
+; X32-NEXT: .Lcfi9:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -458,7 +458,7 @@ define <4 x float> @test_mm_mask_broadca
; X32-LABEL: test_mm_mask_broadcastss_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp10:
+; X32-NEXT: .Lcfi10:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -488,7 +488,7 @@ define <4 x float> @test_mm_maskz_broadc
; X32-LABEL: test_mm_maskz_broadcastss_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp11:
+; X32-NEXT: .Lcfi11:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -584,7 +584,7 @@ define <2 x double> @test_mm_mask_movddu
; X32-LABEL: test_mm_mask_movddup_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp12:
+; X32-NEXT: .Lcfi12:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -614,7 +614,7 @@ define <2 x double> @test_mm_maskz_movdd
; X32-LABEL: test_mm_maskz_movddup_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp13:
+; X32-NEXT: .Lcfi13:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -658,7 +658,7 @@ define <4 x double> @test_mm256_mask_mov
; X32-LABEL: test_mm256_mask_movddup_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp14:
+; X32-NEXT: .Lcfi14:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -688,7 +688,7 @@ define <4 x double> @test_mm256_maskz_mo
; X32-LABEL: test_mm256_maskz_movddup_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp15:
+; X32-NEXT: .Lcfi15:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -732,7 +732,7 @@ define <4 x float> @test_mm_mask_movehdu
; X32-LABEL: test_mm_mask_movehdup_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp16:
+; X32-NEXT: .Lcfi16:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -762,7 +762,7 @@ define <4 x float> @test_mm_maskz_movehd
; X32-LABEL: test_mm_maskz_movehdup_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp17:
+; X32-NEXT: .Lcfi17:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -858,7 +858,7 @@ define <4 x float> @test_mm_mask_moveldu
; X32-LABEL: test_mm_mask_moveldup_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp18:
+; X32-NEXT: .Lcfi18:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -888,7 +888,7 @@ define <4 x float> @test_mm_maskz_moveld
; X32-LABEL: test_mm_maskz_moveldup_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp19:
+; X32-NEXT: .Lcfi19:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -984,7 +984,7 @@ define <4 x i64> @test_mm256_mask_permut
; X32-LABEL: test_mm256_mask_permutex_epi64:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp20:
+; X32-NEXT: .Lcfi20:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1014,7 +1014,7 @@ define <4 x i64> @test_mm256_maskz_permu
; X32-LABEL: test_mm256_maskz_permutex_epi64:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp21:
+; X32-NEXT: .Lcfi21:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1058,7 +1058,7 @@ define <4 x double> @test_mm256_mask_per
; X32-LABEL: test_mm256_mask_permutex_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp22:
+; X32-NEXT: .Lcfi22:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1088,7 +1088,7 @@ define <4 x double> @test_mm256_maskz_pe
; X32-LABEL: test_mm256_maskz_permutex_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp23:
+; X32-NEXT: .Lcfi23:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1132,7 +1132,7 @@ define <2 x double> @test_mm_mask_shuffl
; X32-LABEL: test_mm_mask_shuffle_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp24:
+; X32-NEXT: .Lcfi24:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -1162,7 +1162,7 @@ define <2 x double> @test_mm_maskz_shuff
; X32-LABEL: test_mm_maskz_shuffle_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp25:
+; X32-NEXT: .Lcfi25:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $3, %al
@@ -1206,7 +1206,7 @@ define <4 x double> @test_mm256_mask_shu
; X32-LABEL: test_mm256_mask_shuffle_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp26:
+; X32-NEXT: .Lcfi26:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1236,7 +1236,7 @@ define <4 x double> @test_mm256_maskz_sh
; X32-LABEL: test_mm256_maskz_shuffle_pd:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp27:
+; X32-NEXT: .Lcfi27:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1280,7 +1280,7 @@ define <4 x float> @test_mm_mask_shuffle
; X32-LABEL: test_mm_mask_shuffle_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp28:
+; X32-NEXT: .Lcfi28:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
@@ -1310,7 +1310,7 @@ define <4 x float> @test_mm_maskz_shuffl
; X32-LABEL: test_mm_maskz_shuffle_ps:
; X32: # BB#0:
; X32-NEXT: pushl %eax
-; X32-NEXT: .Ltmp29:
+; X32-NEXT: .Lcfi29:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movb {{[0-9]+}}(%esp), %al
; X32-NEXT: andb $15, %al
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-vbroadcast.ll Wed Nov 30 17:48:26 2016
@@ -6,7 +6,7 @@ define <8 x float> @_256_broadcast_ss_sp
; CHECK-LABEL: _256_broadcast_ss_spill:
; CHECK: # BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
@@ -25,7 +25,7 @@ define <4 x float> @_128_broadcast_ss_sp
; CHECK-LABEL: _128_broadcast_ss_spill:
; CHECK: # BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vaddss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
@@ -45,7 +45,7 @@ define <4 x double> @_256_broadcast_sd_s
; CHECK-LABEL: _256_broadcast_sd_spill:
; CHECK: # BB#0:
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vaddsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
Modified: llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/deopt-intrinsic-cconv.ll Wed Nov 30 17:48:26 2016
@@ -12,7 +12,7 @@ define i64 @caller_1() {
; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: ##{{.+}}
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: {{Ltmp[0-9]+}}:
+; CHECK-NEXT: {{Lcfi[0-9]+}}:
; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: movl $1140457472, (%rsp) ## imm = 0x43FA0000
; CHECK-NEXT: movl $42, %eax
Modified: llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/deopt-intrinsic.ll Wed Nov 30 17:48:26 2016
@@ -13,7 +13,7 @@ define i32 @caller_0() {
; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: ##{{.+}}
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: {{Ltmp[0-9]+}}:
+; CHECK-NEXT: {{Lcfi[0-9]+}}:
; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: callq ___llvm_deoptimize
; CHECK-NEXT: {{Ltmp[0-9]+}}:
@@ -27,7 +27,7 @@ define i8 @caller_1() {
; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: ##{{.+}}
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: {{Ltmp[0-9]+}}:
+; CHECK-NEXT: {{Lcfi[0-9]+}}:
; CHECK-NEXT: {{.+cfi.+}}
; CHECK-NEXT: movss {{[a-zA-Z0-9_]+}}(%rip), %xmm0 ## xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movl $42, %edi
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-store.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-store.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-store.ll Wed Nov 30 17:48:26 2016
@@ -368,7 +368,7 @@ define <4 x double> @test_store_4xf64(<4
; SSE64-LABEL: test_store_4xf64:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp0:
+; SSE64-NEXT: .Lcfi0:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
@@ -407,7 +407,7 @@ define <4 x double> @test_store_4xf64_al
; SSE64-LABEL: test_store_4xf64_aligned:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp1:
+; SSE64-NEXT: .Lcfi1:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE64-NEXT: addpd {{[0-9]+}}(%esp), %xmm1
@@ -446,7 +446,7 @@ define <16 x i32> @test_store_16xi32(<16
; SSE64-LABEL: test_store_16xi32:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp2:
+; SSE64-NEXT: .Lcfi2:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -496,7 +496,7 @@ define <16 x i32> @test_store_16xi32_ali
; SSE64-LABEL: test_store_16xi32_aligned:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp3:
+; SSE64-NEXT: .Lcfi3:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -546,7 +546,7 @@ define <16 x float> @test_store_16xf32(<
; SSE64-LABEL: test_store_16xf32:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp4:
+; SSE64-NEXT: .Lcfi4:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -596,7 +596,7 @@ define <16 x float> @test_store_16xf32_a
; SSE64-LABEL: test_store_16xf32_aligned:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp5:
+; SSE64-NEXT: .Lcfi5:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movaps {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -650,7 +650,7 @@ define <8 x double> @test_store_8xf64(<8
; SSE64-LABEL: test_store_8xf64:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp6:
+; SSE64-NEXT: .Lcfi6:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -676,12 +676,12 @@ define <8 x double> @test_store_8xf64(<8
; AVXONLY64-LABEL: test_store_8xf64:
; AVXONLY64: # BB#0:
; AVXONLY64-NEXT: pushl %ebp
-; AVXONLY64-NEXT: .Ltmp0:
+; AVXONLY64-NEXT: .Lcfi0:
; AVXONLY64-NEXT: .cfi_def_cfa_offset 8
-; AVXONLY64-NEXT: .Ltmp1:
+; AVXONLY64-NEXT: .Lcfi1:
; AVXONLY64-NEXT: .cfi_offset %ebp, -8
; AVXONLY64-NEXT: movl %esp, %ebp
-; AVXONLY64-NEXT: .Ltmp2:
+; AVXONLY64-NEXT: .Lcfi2:
; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp
; AVXONLY64-NEXT: andl $-32, %esp
; AVXONLY64-NEXT: subl $32, %esp
@@ -727,7 +727,7 @@ define <8 x double> @test_store_8xf64_al
; SSE64-LABEL: test_store_8xf64_aligned:
; SSE64: # BB#0:
; SSE64-NEXT: subl $12, %esp
-; SSE64-NEXT: .Ltmp7:
+; SSE64-NEXT: .Lcfi7:
; SSE64-NEXT: .cfi_def_cfa_offset 16
; SSE64-NEXT: movapd {{[0-9]+}}(%esp), %xmm3
; SSE64-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -753,12 +753,12 @@ define <8 x double> @test_store_8xf64_al
; AVXONLY64-LABEL: test_store_8xf64_aligned:
; AVXONLY64: # BB#0:
; AVXONLY64-NEXT: pushl %ebp
-; AVXONLY64-NEXT: .Ltmp3:
+; AVXONLY64-NEXT: .Lcfi3:
; AVXONLY64-NEXT: .cfi_def_cfa_offset 8
-; AVXONLY64-NEXT: .Ltmp4:
+; AVXONLY64-NEXT: .Lcfi4:
; AVXONLY64-NEXT: .cfi_offset %ebp, -8
; AVXONLY64-NEXT: movl %esp, %ebp
-; AVXONLY64-NEXT: .Ltmp5:
+; AVXONLY64-NEXT: .Lcfi5:
; AVXONLY64-NEXT: .cfi_def_cfa_register %ebp
; AVXONLY64-NEXT: andl $-32, %esp
; AVXONLY64-NEXT: subl $32, %esp
Modified: llvm/trunk/test/CodeGen/X86/haddsub-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/haddsub-2.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/haddsub-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/haddsub-2.ll Wed Nov 30 17:48:26 2016
@@ -624,34 +624,34 @@ define <16 x i16> @avx2_vphadd_w_test(<1
; SSE3-LABEL: avx2_vphadd_w_test:
; SSE3: # BB#0:
; SSE3-NEXT: pushq %rbp
-; SSE3-NEXT: .Ltmp0:
+; SSE3-NEXT: .Lcfi0:
; SSE3-NEXT: .cfi_def_cfa_offset 16
; SSE3-NEXT: pushq %r15
-; SSE3-NEXT: .Ltmp1:
+; SSE3-NEXT: .Lcfi1:
; SSE3-NEXT: .cfi_def_cfa_offset 24
; SSE3-NEXT: pushq %r14
-; SSE3-NEXT: .Ltmp2:
+; SSE3-NEXT: .Lcfi2:
; SSE3-NEXT: .cfi_def_cfa_offset 32
; SSE3-NEXT: pushq %r13
-; SSE3-NEXT: .Ltmp3:
+; SSE3-NEXT: .Lcfi3:
; SSE3-NEXT: .cfi_def_cfa_offset 40
; SSE3-NEXT: pushq %r12
-; SSE3-NEXT: .Ltmp4:
+; SSE3-NEXT: .Lcfi4:
; SSE3-NEXT: .cfi_def_cfa_offset 48
; SSE3-NEXT: pushq %rbx
-; SSE3-NEXT: .Ltmp5:
+; SSE3-NEXT: .Lcfi5:
; SSE3-NEXT: .cfi_def_cfa_offset 56
-; SSE3-NEXT: .Ltmp6:
+; SSE3-NEXT: .Lcfi6:
; SSE3-NEXT: .cfi_offset %rbx, -56
-; SSE3-NEXT: .Ltmp7:
+; SSE3-NEXT: .Lcfi7:
; SSE3-NEXT: .cfi_offset %r12, -48
-; SSE3-NEXT: .Ltmp8:
+; SSE3-NEXT: .Lcfi8:
; SSE3-NEXT: .cfi_offset %r13, -40
-; SSE3-NEXT: .Ltmp9:
+; SSE3-NEXT: .Lcfi9:
; SSE3-NEXT: .cfi_offset %r14, -32
-; SSE3-NEXT: .Ltmp10:
+; SSE3-NEXT: .Lcfi10:
; SSE3-NEXT: .cfi_offset %r15, -24
-; SSE3-NEXT: .Ltmp11:
+; SSE3-NEXT: .Lcfi11:
; SSE3-NEXT: .cfi_offset %rbp, -16
; SSE3-NEXT: movd %xmm0, %eax
; SSE3-NEXT: pextrw $1, %xmm0, %ecx
@@ -1263,34 +1263,34 @@ define <16 x i16> @avx2_hadd_w(<16 x i16
; SSE3-LABEL: avx2_hadd_w:
; SSE3: # BB#0:
; SSE3-NEXT: pushq %rbp
-; SSE3-NEXT: .Ltmp12:
+; SSE3-NEXT: .Lcfi12:
; SSE3-NEXT: .cfi_def_cfa_offset 16
; SSE3-NEXT: pushq %r15
-; SSE3-NEXT: .Ltmp13:
+; SSE3-NEXT: .Lcfi13:
; SSE3-NEXT: .cfi_def_cfa_offset 24
; SSE3-NEXT: pushq %r14
-; SSE3-NEXT: .Ltmp14:
+; SSE3-NEXT: .Lcfi14:
; SSE3-NEXT: .cfi_def_cfa_offset 32
; SSE3-NEXT: pushq %r13
-; SSE3-NEXT: .Ltmp15:
+; SSE3-NEXT: .Lcfi15:
; SSE3-NEXT: .cfi_def_cfa_offset 40
; SSE3-NEXT: pushq %r12
-; SSE3-NEXT: .Ltmp16:
+; SSE3-NEXT: .Lcfi16:
; SSE3-NEXT: .cfi_def_cfa_offset 48
; SSE3-NEXT: pushq %rbx
-; SSE3-NEXT: .Ltmp17:
+; SSE3-NEXT: .Lcfi17:
; SSE3-NEXT: .cfi_def_cfa_offset 56
-; SSE3-NEXT: .Ltmp18:
+; SSE3-NEXT: .Lcfi18:
; SSE3-NEXT: .cfi_offset %rbx, -56
-; SSE3-NEXT: .Ltmp19:
+; SSE3-NEXT: .Lcfi19:
; SSE3-NEXT: .cfi_offset %r12, -48
-; SSE3-NEXT: .Ltmp20:
+; SSE3-NEXT: .Lcfi20:
; SSE3-NEXT: .cfi_offset %r13, -40
-; SSE3-NEXT: .Ltmp21:
+; SSE3-NEXT: .Lcfi21:
; SSE3-NEXT: .cfi_offset %r14, -32
-; SSE3-NEXT: .Ltmp22:
+; SSE3-NEXT: .Lcfi22:
; SSE3-NEXT: .cfi_offset %r15, -24
-; SSE3-NEXT: .Ltmp23:
+; SSE3-NEXT: .Lcfi23:
; SSE3-NEXT: .cfi_offset %rbp, -16
; SSE3-NEXT: movd %xmm0, %eax
; SSE3-NEXT: pextrw $1, %xmm0, %ecx
Modified: llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll Wed Nov 30 17:48:26 2016
@@ -76,24 +76,24 @@ define <2 x i64> @test5(<2 x i64> %A, <2
; CHECK-LABEL: test5:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %ebx
-; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: pushl %edi
-; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushl %esi
-; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_def_cfa_offset 20
-; CHECK-NEXT: .Ltmp4:
+; CHECK-NEXT: .Lcfi4:
; CHECK-NEXT: .cfi_offset %esi, -20
-; CHECK-NEXT: .Ltmp5:
+; CHECK-NEXT: .Lcfi5:
; CHECK-NEXT: .cfi_offset %edi, -16
-; CHECK-NEXT: .Ltmp6:
+; CHECK-NEXT: .Lcfi6:
; CHECK-NEXT: .cfi_offset %ebx, -12
-; CHECK-NEXT: .Ltmp7:
+; CHECK-NEXT: .Lcfi7:
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
@@ -138,12 +138,12 @@ define i32 @test6() {
; CHECK-LABEL: test6:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp
-; CHECK-NEXT: .Ltmp8:
+; CHECK-NEXT: .Lcfi8:
; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: .Ltmp9:
+; CHECK-NEXT: .Lcfi9:
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp
-; CHECK-NEXT: .Ltmp10:
+; CHECK-NEXT: .Lcfi10:
; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp
Modified: llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll (original)
+++ llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll Wed Nov 30 17:48:26 2016
@@ -1663,12 +1663,12 @@ define <16 x i64> @test_gather_16i64(<16
; KNL_32-LABEL: test_gather_16i64:
; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp
-; KNL_32-NEXT: .Ltmp0:
+; KNL_32-NEXT: .Lcfi0:
; KNL_32-NEXT: .cfi_def_cfa_offset 8
-; KNL_32-NEXT: .Ltmp1:
+; KNL_32-NEXT: .Lcfi1:
; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp
-; KNL_32-NEXT: .Ltmp2:
+; KNL_32-NEXT: .Lcfi2:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp
@@ -1700,12 +1700,12 @@ define <16 x i64> @test_gather_16i64(<16
; SKX_32-LABEL: test_gather_16i64:
; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp
-; SKX_32-NEXT: .Ltmp1:
+; SKX_32-NEXT: .Lcfi1:
; SKX_32-NEXT: .cfi_def_cfa_offset 8
-; SKX_32-NEXT: .Ltmp2:
+; SKX_32-NEXT: .Lcfi2:
; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp
-; SKX_32-NEXT: .Ltmp3:
+; SKX_32-NEXT: .Lcfi3:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp
@@ -1786,12 +1786,12 @@ define <16 x double> @test_gather_16f64(
; KNL_32-LABEL: test_gather_16f64:
; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp
-; KNL_32-NEXT: .Ltmp3:
+; KNL_32-NEXT: .Lcfi3:
; KNL_32-NEXT: .cfi_def_cfa_offset 8
-; KNL_32-NEXT: .Ltmp4:
+; KNL_32-NEXT: .Lcfi4:
; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp
-; KNL_32-NEXT: .Ltmp5:
+; KNL_32-NEXT: .Lcfi5:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp
@@ -1823,12 +1823,12 @@ define <16 x double> @test_gather_16f64(
; SKX_32-LABEL: test_gather_16f64:
; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp
-; SKX_32-NEXT: .Ltmp4:
+; SKX_32-NEXT: .Lcfi4:
; SKX_32-NEXT: .cfi_def_cfa_offset 8
-; SKX_32-NEXT: .Ltmp5:
+; SKX_32-NEXT: .Lcfi5:
; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp
-; SKX_32-NEXT: .Ltmp6:
+; SKX_32-NEXT: .Lcfi6:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp
@@ -1903,12 +1903,12 @@ define void @test_scatter_16i64(<16 x i6
; KNL_32-LABEL: test_scatter_16i64:
; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp
-; KNL_32-NEXT: .Ltmp6:
+; KNL_32-NEXT: .Lcfi6:
; KNL_32-NEXT: .cfi_def_cfa_offset 8
-; KNL_32-NEXT: .Ltmp7:
+; KNL_32-NEXT: .Lcfi7:
; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp
-; KNL_32-NEXT: .Ltmp8:
+; KNL_32-NEXT: .Lcfi8:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp
@@ -1937,12 +1937,12 @@ define void @test_scatter_16i64(<16 x i6
; SKX_32-LABEL: test_scatter_16i64:
; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp
-; SKX_32-NEXT: .Ltmp7:
+; SKX_32-NEXT: .Lcfi7:
; SKX_32-NEXT: .cfi_def_cfa_offset 8
-; SKX_32-NEXT: .Ltmp8:
+; SKX_32-NEXT: .Lcfi8:
; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp
-; SKX_32-NEXT: .Ltmp9:
+; SKX_32-NEXT: .Lcfi9:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp
@@ -2017,12 +2017,12 @@ define void @test_scatter_16f64(<16 x do
; KNL_32-LABEL: test_scatter_16f64:
; KNL_32: # BB#0:
; KNL_32-NEXT: pushl %ebp
-; KNL_32-NEXT: .Ltmp9:
+; KNL_32-NEXT: .Lcfi9:
; KNL_32-NEXT: .cfi_def_cfa_offset 8
-; KNL_32-NEXT: .Ltmp10:
+; KNL_32-NEXT: .Lcfi10:
; KNL_32-NEXT: .cfi_offset %ebp, -8
; KNL_32-NEXT: movl %esp, %ebp
-; KNL_32-NEXT: .Ltmp11:
+; KNL_32-NEXT: .Lcfi11:
; KNL_32-NEXT: .cfi_def_cfa_register %ebp
; KNL_32-NEXT: andl $-64, %esp
; KNL_32-NEXT: subl $64, %esp
@@ -2051,12 +2051,12 @@ define void @test_scatter_16f64(<16 x do
; SKX_32-LABEL: test_scatter_16f64:
; SKX_32: # BB#0:
; SKX_32-NEXT: pushl %ebp
-; SKX_32-NEXT: .Ltmp10:
+; SKX_32-NEXT: .Lcfi10:
; SKX_32-NEXT: .cfi_def_cfa_offset 8
-; SKX_32-NEXT: .Ltmp11:
+; SKX_32-NEXT: .Lcfi11:
; SKX_32-NEXT: .cfi_offset %ebp, -8
; SKX_32-NEXT: movl %esp, %ebp
-; SKX_32-NEXT: .Ltmp12:
+; SKX_32-NEXT: .Lcfi12:
; SKX_32-NEXT: .cfi_def_cfa_register %ebp
; SKX_32-NEXT: andl $-64, %esp
; SKX_32-NEXT: subl $64, %esp
Modified: llvm/trunk/test/CodeGen/X86/memset-nonzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memset-nonzero.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memset-nonzero.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memset-nonzero.ll Wed Nov 30 17:48:26 2016
@@ -147,7 +147,7 @@ define void @memset_256_nonzero_bytes(i8
; SSE-LABEL: memset_256_nonzero_bytes:
; SSE: # BB#0:
; SSE-NEXT: pushq %rax
-; SSE-NEXT: .Ltmp0:
+; SSE-NEXT: .Lcfi0:
; SSE-NEXT: .cfi_def_cfa_offset 16
; SSE-NEXT: movl $42, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll Wed Nov 30 17:48:26 2016
@@ -56,14 +56,14 @@ define <2 x i64> @merge_2i64_i64_12(i64*
; X32-SSE1-LABEL: merge_2i64_i64_12:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi
-; X32-SSE1-NEXT: .Ltmp0:
+; X32-SSE1-NEXT: .Lcfi0:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi
-; X32-SSE1-NEXT: .Ltmp1:
+; X32-SSE1-NEXT: .Lcfi1:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT: .Ltmp2:
+; X32-SSE1-NEXT: .Lcfi2:
; X32-SSE1-NEXT: .cfi_offset %esi, -12
-; X32-SSE1-NEXT: .Ltmp3:
+; X32-SSE1-NEXT: .Lcfi3:
; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -381,9 +381,9 @@ define <4 x i32> @merge_4i32_i32_23u5(i3
; X32-SSE1-LABEL: merge_4i32_i32_23u5:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %esi
-; X32-SSE1-NEXT: .Ltmp4:
+; X32-SSE1-NEXT: .Lcfi4:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
-; X32-SSE1-NEXT: .Ltmp5:
+; X32-SSE1-NEXT: .Lcfi5:
; X32-SSE1-NEXT: .cfi_offset %esi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -531,24 +531,24 @@ define <8 x i16> @merge_8i16_i16_23u567u
; X32-SSE1-LABEL: merge_8i16_i16_23u567u9:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %ebp
-; X32-SSE1-NEXT: .Ltmp6:
+; X32-SSE1-NEXT: .Lcfi6:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %ebx
-; X32-SSE1-NEXT: .Ltmp7:
+; X32-SSE1-NEXT: .Lcfi7:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
; X32-SSE1-NEXT: pushl %edi
-; X32-SSE1-NEXT: .Ltmp8:
+; X32-SSE1-NEXT: .Lcfi8:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 16
; X32-SSE1-NEXT: pushl %esi
-; X32-SSE1-NEXT: .Ltmp9:
+; X32-SSE1-NEXT: .Lcfi9:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 20
-; X32-SSE1-NEXT: .Ltmp10:
+; X32-SSE1-NEXT: .Lcfi10:
; X32-SSE1-NEXT: .cfi_offset %esi, -20
-; X32-SSE1-NEXT: .Ltmp11:
+; X32-SSE1-NEXT: .Lcfi11:
; X32-SSE1-NEXT: .cfi_offset %edi, -16
-; X32-SSE1-NEXT: .Ltmp12:
+; X32-SSE1-NEXT: .Lcfi12:
; X32-SSE1-NEXT: .cfi_offset %ebx, -12
-; X32-SSE1-NEXT: .Ltmp13:
+; X32-SSE1-NEXT: .Lcfi13:
; X32-SSE1-NEXT: .cfi_offset %ebp, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -645,9 +645,9 @@ define <8 x i16> @merge_8i16_i16_45u7zzz
; X32-SSE1-LABEL: merge_8i16_i16_45u7zzzz:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %esi
-; X32-SSE1-NEXT: .Ltmp14:
+; X32-SSE1-NEXT: .Lcfi14:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
-; X32-SSE1-NEXT: .Ltmp15:
+; X32-SSE1-NEXT: .Lcfi15:
; X32-SSE1-NEXT: .cfi_offset %esi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -699,12 +699,12 @@ define <16 x i8> @merge_16i8_i8_01u34567
; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %ebx
-; X32-SSE1-NEXT: .Ltmp16:
+; X32-SSE1-NEXT: .Lcfi16:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: subl $12, %esp
-; X32-SSE1-NEXT: .Ltmp17:
+; X32-SSE1-NEXT: .Lcfi17:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 20
-; X32-SSE1-NEXT: .Ltmp18:
+; X32-SSE1-NEXT: .Lcfi18:
; X32-SSE1-NEXT: .cfi_offset %ebx, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -872,12 +872,12 @@ define <16 x i8> @merge_16i8_i8_0123uu67
; X32-SSE1-LABEL: merge_16i8_i8_0123uu67uuuuuzzz:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %ebx
-; X32-SSE1-NEXT: .Ltmp19:
+; X32-SSE1-NEXT: .Lcfi19:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %eax
-; X32-SSE1-NEXT: .Ltmp20:
+; X32-SSE1-NEXT: .Lcfi20:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT: .Ltmp21:
+; X32-SSE1-NEXT: .Lcfi21:
; X32-SSE1-NEXT: .cfi_offset %ebx, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -1006,14 +1006,14 @@ define <2 x i64> @merge_2i64_i64_12_vola
; X32-SSE1-LABEL: merge_2i64_i64_12_volatile:
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %edi
-; X32-SSE1-NEXT: .Ltmp22:
+; X32-SSE1-NEXT: .Lcfi22:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
; X32-SSE1-NEXT: pushl %esi
-; X32-SSE1-NEXT: .Ltmp23:
+; X32-SSE1-NEXT: .Lcfi23:
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT: .Ltmp24:
+; X32-SSE1-NEXT: .Lcfi24:
; X32-SSE1-NEXT: .cfi_offset %esi, -12
-; X32-SSE1-NEXT: .Ltmp25:
+; X32-SSE1-NEXT: .Lcfi25:
; X32-SSE1-NEXT: .cfi_offset %edi, -8
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
Modified: llvm/trunk/test/CodeGen/X86/movpc32-check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movpc32-check.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movpc32-check.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movpc32-check.ll Wed Nov 30 17:48:26 2016
@@ -33,9 +33,9 @@ attributes #1 = { "disable-tail-calls"="
!12 = !DILocation(line: 5, column: 1, scope: !4)
; CHECK: calll .L0$pb
-; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: .L0$pb:
; CHECK-NEXT: popl
-; CHECK-NEXT: .Ltmp4:
+; CHECK-NEXT: .Lcfi4:
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
Modified: llvm/trunk/test/CodeGen/X86/patchpoint-webkit_jscc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/patchpoint-webkit_jscc.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/patchpoint-webkit_jscc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/patchpoint-webkit_jscc.ll Wed Nov 30 17:48:26 2016
@@ -7,7 +7,7 @@
define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen:
-; CHECK: Ltmp
+; CHECK: Lcfi
; CHECK: movq %r{{.+}}, (%rsp)
; CHECK: movq %r{{.+}}, %rax
; CHECK: Ltmp
@@ -16,7 +16,7 @@ entry:
; CHECK: movq %rax, (%rsp)
; CHECK: callq
; FAST-LABEL: jscall_patchpoint_codegen:
-; FAST: Ltmp
+; FAST: Lcfi
; FAST: movq %r{{.+}}, (%rsp)
; FAST: movq %r{{.+}}, %rax
; FAST: Ltmp
@@ -35,7 +35,7 @@ entry:
define i64 @jscall_patchpoint_codegen2(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK: Ltmp
+; CHECK: Lcfi
; CHECK: movq $6, 24(%rsp)
; CHECK-NEXT: movl $4, 16(%rsp)
; CHECK-NEXT: movq $2, (%rsp)
@@ -43,7 +43,7 @@ entry:
; CHECK-NEXT: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11
; FAST-LABEL: jscall_patchpoint_codegen2:
-; FAST: Ltmp
+; FAST: Lcfi
; FAST: movq $2, (%rsp)
; FAST-NEXT: movl $4, 16(%rsp)
; FAST-NEXT: movq $6, 24(%rsp)
@@ -59,7 +59,7 @@ entry:
define i64 @jscall_patchpoint_codegen3(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen3:
-; CHECK: Ltmp
+; CHECK: Lcfi
; CHECK: movq $10, 48(%rsp)
; CHECK-NEXT: movl $8, 36(%rsp)
; CHECK-NEXT: movq $6, 24(%rsp)
@@ -69,7 +69,7 @@ entry:
; CHECK-NEXT: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11
; FAST-LABEL: jscall_patchpoint_codegen3:
-; FAST: Ltmp
+; FAST: Lcfi
; FAST: movq $2, (%rsp)
; FAST-NEXT: movl $4, 16(%rsp)
; FAST-NEXT: movq $6, 24(%rsp)
Modified: llvm/trunk/test/CodeGen/X86/pr27071.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr27071.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr27071.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr27071.ll Wed Nov 30 17:48:26 2016
@@ -23,7 +23,7 @@ declare void @x2(i8*)
attributes #0 = { optsize }
; CHECK-LABEL: x3:
-; CHECK: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp4-.L0$pb), %[[REG:.*]]
+; CHECK: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %[[REG:.*]]
; CHECK-NEXT: leal x1 at TLSGD(,%[[REG]]), %eax
; CHECK-NEXT: calll ___tls_get_addr at PLT
; CHECK-NEXT: cmpl $92, (%eax)
Modified: llvm/trunk/test/CodeGen/X86/pr29112.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr29112.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr29112.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr29112.ll Wed Nov 30 17:48:26 2016
@@ -9,7 +9,7 @@ define <4 x float> @bar(<4 x float>* %a1
; CHECK-LABEL: bar:
; CHECK: # BB#0:
; CHECK-NEXT: subq $88, %rsp
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
; CHECK-NEXT: vextractf32x4 $1, %zmm3, %xmm1
Modified: llvm/trunk/test/CodeGen/X86/pr30430.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr30430.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr30430.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr30430.ll Wed Nov 30 17:48:26 2016
@@ -5,12 +5,12 @@ define <16 x float> @makefloat(float %f1
; CHECK-LABEL: makefloat:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: pushq %rbp
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp
-; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: andq $-64, %rsp
; CHECK-NEXT: subq $256, %rsp # imm = 0x100
Modified: llvm/trunk/test/CodeGen/X86/push-cfi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/push-cfi.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/push-cfi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/push-cfi.ll Wed Nov 30 17:48:26 2016
@@ -13,16 +13,16 @@ declare void @empty()
; CHECK-LABEL: test1_nofp:
; LINUX: .cfi_escape 0x2e, 0x10
; LINUX-NEXT: pushl $4
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $3
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $2
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $1
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: call
; LINUX-NEXT: addl $16, %esp
@@ -70,16 +70,16 @@ cleanup:
; CHECK-LABEL: test2_nofp:
; LINUX-NOT: .cfi_escape
; LINUX: pushl $4
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $3
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $2
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $1
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: call
; LINUX-NEXT: addl $28, %esp
@@ -185,16 +185,16 @@ cleanup:
; CHECK-LABEL: test5_nofp:
; LINUX: .cfi_escape 0x2e, 0x10
; LINUX-NEXT: pushl $4
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $3
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $2
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: pushl $1
-; LINUX-NEXT: Ltmp{{[0-9]+}}:
+; LINUX-NEXT: Lcfi{{[0-9]+}}:
; LINUX-NEXT: .cfi_adjust_cfa_offset 4
; LINUX-NEXT: call
; LINUX-NEXT: addl $16, %esp
Modified: llvm/trunk/test/CodeGen/X86/setcc-lowering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc-lowering.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/setcc-lowering.ll (original)
+++ llvm/trunk/test/CodeGen/X86/setcc-lowering.ll Wed Nov 30 17:48:26 2016
@@ -32,9 +32,9 @@ define void @pr26232(i64 %a) {
; KNL-32-LABEL: pr26232:
; KNL-32: # BB#0: # %for_loop599.preheader
; KNL-32-NEXT: pushl %esi
-; KNL-32-NEXT: .Ltmp0:
+; KNL-32-NEXT: .Lcfi0:
; KNL-32-NEXT: .cfi_def_cfa_offset 8
-; KNL-32-NEXT: .Ltmp1:
+; KNL-32-NEXT: .Lcfi1:
; KNL-32-NEXT: .cfi_offset %esi, -8
; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
Modified: llvm/trunk/test/CodeGen/X86/statepoint-allocas.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-allocas.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/statepoint-allocas.ll (original)
+++ llvm/trunk/test/CodeGen/X86/statepoint-allocas.ll Wed Nov 30 17:48:26 2016
@@ -72,7 +72,7 @@ declare token @llvm.experimental.gc.stat
; Callsites
; The GC one
-; CHECK: .long .Ltmp1-test
+; CHECK: .long .Ltmp0-test
; CHECK: .short 0
; CHECK: .short 4
; SmallConstant (0)
@@ -101,7 +101,7 @@ declare token @llvm.experimental.gc.stat
; CHECK: .p2align 3
; The Deopt one
-; CHECK: .long .Ltmp3-test2
+; CHECK: .long .Ltmp1-test2
; CHECK: .short 0
; CHECK: .short 4
; SmallConstant (0)
Modified: llvm/trunk/test/CodeGen/X86/statepoint-call-lowering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-call-lowering.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/statepoint-call-lowering.ll (original)
+++ llvm/trunk/test/CodeGen/X86/statepoint-call-lowering.ll Wed Nov 30 17:48:26 2016
@@ -81,7 +81,7 @@ define i1 @test_relocate(i32 addrspace(1
; Check that an ununsed relocate has no code-generation impact
; CHECK: pushq %rax
; CHECK: callq return_i1
-; CHECK-NEXT: .Ltmp11:
+; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
entry:
Modified: llvm/trunk/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll (original)
+++ llvm/trunk/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll Wed Nov 30 17:48:26 2016
@@ -67,7 +67,7 @@ define i1 @test_relocate(i32 addrspace(1
; Check that an ununsed relocate has no code-generation impact
; CHECK: pushq %rax
; CHECK: callq return_i1
-; CHECK-NEXT: .Ltmp9:
+; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
entry:
@@ -130,4 +130,4 @@ declare float @llvm.experimental.gc.resu
declare token @llvm.experimental.gc.statepoint.p0f_isVoidi32varargf(i64, i32, void (i32, ...)*, i32, i32, ...)
-declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32)
\ No newline at end of file
+declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32)
Modified: llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll (original)
+++ llvm/trunk/test/CodeGen/X86/statepoint-live-in.ll Wed Nov 30 17:48:26 2016
@@ -10,7 +10,7 @@ entry:
; We expect the argument to be passed in an extra register to bar
; CHECK-LABEL: test1
; CHECK: pushq %rax
-; CHECK-NEXT: Ltmp0:
+; CHECK-NEXT: Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq _bar
%statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
@@ -90,7 +90,7 @@ entry:
; CHECK: movl %edi, %ebx
; CHECK: movl %ebx, 12(%rsp)
; CHECK-NEXT: callq _baz
-; CHECK-NEXT: Ltmp30:
+; CHECK-NEXT: Ltmp6:
; CHECK-NEXT: callq _bar
call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @baz, i32 0, i32 0, i32 0, i32 1, i32 %a)
call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a)
@@ -98,13 +98,13 @@ entry:
}
-; CHECK: Ltmp1-_test1
+; CHECK: Ltmp0-_test1
; CHECK: .byte 1
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .short 5
; CHECK-NEXT: .long 0
-; CHECK: Ltmp7-_test2
+; CHECK: Ltmp1-_test2
; CHECK: .byte 1
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .short 6
@@ -113,7 +113,7 @@ entry:
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .short 3
; CHECK-NEXT: .long 0
-; CHECK: Ltmp8-_test2
+; CHECK: Ltmp2-_test2
; CHECK: .byte 1
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .short 3
Modified: llvm/trunk/test/CodeGen/X86/statepoint-stackmap-format.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-stackmap-format.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/statepoint-stackmap-format.ll (original)
+++ llvm/trunk/test/CodeGen/X86/statepoint-stackmap-format.ll Wed Nov 30 17:48:26 2016
@@ -109,7 +109,7 @@ declare i32 addrspace(1)* @llvm.experime
; Callsites
; Constant arguments
-; CHECK-NEXT: .long .Ltmp1-test
+; CHECK-NEXT: .long .Ltmp0-test
; CHECK: .short 0
; CHECK: .short 11
; SmallConstant (0)
@@ -181,7 +181,7 @@ declare i32 addrspace(1)* @llvm.experime
; Callsites
; Constant arguments
-; CHECK-NEXT: .long .Ltmp3-test_derived_arg
+; CHECK-NEXT: .long .Ltmp1-test_derived_arg
; CHECK: .short 0
; CHECK: .short 11
; SmallConstant (0)
@@ -246,7 +246,7 @@ declare i32 addrspace(1)* @llvm.experime
; CHECK-NEXT: .quad 237
; Instruction Offset
-; CHECK-NEXT: .long .Ltmp5-test_id
+; CHECK-NEXT: .long .Ltmp2-test_id
; Reserved:
; CHECK: .short 0
Modified: llvm/trunk/test/CodeGen/X86/statepoint-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-vector.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/statepoint-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/statepoint-vector.ll Wed Nov 30 17:48:26 2016
@@ -106,7 +106,7 @@ entry:
; CHECK: __LLVM_StackMaps:
-; CHECK: .Ltmp1-test
+; CHECK: .Ltmp0-test
; Check for the two spill slots
; Stack Maps: Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
; Stack Maps: Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
@@ -119,7 +119,7 @@ entry:
; CHECK: .short 7
; CHECK: .long 0
-; CHECK: .Ltmp3-test2
+; CHECK: .Ltmp1-test2
; Check for the two spill slots
; Stack Maps: Loc 3: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16]
; Stack Maps: Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0]
@@ -132,7 +132,7 @@ entry:
; CHECK: .short 7
; CHECK: .long 0
-; CHECK: .Ltmp5-test3
+; CHECK: .Ltmp2-test3
; Check for the four spill slots
; Stack Maps: Loc 3: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16]
; Stack Maps: Loc 4: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16]
Modified: llvm/trunk/test/CodeGen/X86/tls-pie.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls-pie.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls-pie.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls-pie.ll Wed Nov 30 17:48:26 2016
@@ -36,11 +36,11 @@ entry:
define i32 @f3() {
; X32-LABEL: f3:
; X32: calll .L{{[0-9]+}}$pb
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
; X32-NEXT: .cfi_adjust_cfa_offset 4
; X32-NEXT: .L{{[0-9]+}}$pb:
; X32-NEXT: popl %eax
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
; X32-NEXT: .cfi_adjust_cfa_offset -4
; X32-NEXT: .Ltmp{{[0-9]+}}:
; X32-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp{{[0-9]+}}-.L{{[0-9]+}}$pb), %eax
@@ -60,11 +60,11 @@ entry:
define i32* @f4() {
; X32-LABEL: f4:
; X32: calll .L{{[0-9]+}}$pb
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
; X32-NEXT: .cfi_adjust_cfa_offset 4
; X32-NEXT: .L{{[0-9]+}}$pb:
; X32-NEXT: popl %ecx
-; X32-NEXT: .Ltmp{{[0-9]+}}:
+; X32-NEXT: .Lcfi{{[0-9]+}}:
; X32-NEXT: .cfi_adjust_cfa_offset -4
; X32-NEXT: .Ltmp{{[0-9]+}}:
; X32-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp{{[0-9]+}}-.L{{[0-9]+}}$pb), %ecx
Modified: llvm/trunk/test/CodeGen/X86/tls-shrink-wrapping.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls-shrink-wrapping.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls-shrink-wrapping.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tls-shrink-wrapping.ll Wed Nov 30 17:48:26 2016
@@ -39,16 +39,16 @@ if.end:
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: # BB#0: # %entry
; CHECK-NEXT: pushq %rbp
-; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: .Ltmp1:
+; CHECK-NEXT: .Lcfi1:
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp
-; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: .Lcfi2:
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .Ltmp3:
+; CHECK-NEXT: .Lcfi3:
; CHECK-NEXT: .cfi_offset %rbx, -24
; CHECK-NEXT: data16
; CHECK-NEXT: leaq i at TLSGD(%rip), %rdi
Modified: llvm/trunk/test/CodeGen/X86/vector-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-sext.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-sext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-sext.ll Wed Nov 30 17:48:26 2016
@@ -3192,34 +3192,34 @@ define <16 x i16> @load_sext_16i1_to_16i
; AVX1-LABEL: load_sext_16i1_to_16i16:
; AVX1: # BB#0: # %entry
; AVX1-NEXT: pushq %rbp
-; AVX1-NEXT: .Ltmp0:
+; AVX1-NEXT: .Lcfi0:
; AVX1-NEXT: .cfi_def_cfa_offset 16
; AVX1-NEXT: pushq %r15
-; AVX1-NEXT: .Ltmp1:
+; AVX1-NEXT: .Lcfi1:
; AVX1-NEXT: .cfi_def_cfa_offset 24
; AVX1-NEXT: pushq %r14
-; AVX1-NEXT: .Ltmp2:
+; AVX1-NEXT: .Lcfi2:
; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX1-NEXT: pushq %r13
-; AVX1-NEXT: .Ltmp3:
+; AVX1-NEXT: .Lcfi3:
; AVX1-NEXT: .cfi_def_cfa_offset 40
; AVX1-NEXT: pushq %r12
-; AVX1-NEXT: .Ltmp4:
+; AVX1-NEXT: .Lcfi4:
; AVX1-NEXT: .cfi_def_cfa_offset 48
; AVX1-NEXT: pushq %rbx
-; AVX1-NEXT: .Ltmp5:
+; AVX1-NEXT: .Lcfi5:
; AVX1-NEXT: .cfi_def_cfa_offset 56
-; AVX1-NEXT: .Ltmp6:
+; AVX1-NEXT: .Lcfi6:
; AVX1-NEXT: .cfi_offset %rbx, -56
-; AVX1-NEXT: .Ltmp7:
+; AVX1-NEXT: .Lcfi7:
; AVX1-NEXT: .cfi_offset %r12, -48
-; AVX1-NEXT: .Ltmp8:
+; AVX1-NEXT: .Lcfi8:
; AVX1-NEXT: .cfi_offset %r13, -40
-; AVX1-NEXT: .Ltmp9:
+; AVX1-NEXT: .Lcfi9:
; AVX1-NEXT: .cfi_offset %r14, -32
-; AVX1-NEXT: .Ltmp10:
+; AVX1-NEXT: .Lcfi10:
; AVX1-NEXT: .cfi_offset %r15, -24
-; AVX1-NEXT: .Ltmp11:
+; AVX1-NEXT: .Lcfi11:
; AVX1-NEXT: .cfi_offset %rbp, -16
; AVX1-NEXT: movswq (%rdi), %rax
; AVX1-NEXT: movq %rax, %rcx
@@ -3295,34 +3295,34 @@ define <16 x i16> @load_sext_16i1_to_16i
; AVX2-LABEL: load_sext_16i1_to_16i16:
; AVX2: # BB#0: # %entry
; AVX2-NEXT: pushq %rbp
-; AVX2-NEXT: .Ltmp0:
+; AVX2-NEXT: .Lcfi0:
; AVX2-NEXT: .cfi_def_cfa_offset 16
; AVX2-NEXT: pushq %r15
-; AVX2-NEXT: .Ltmp1:
+; AVX2-NEXT: .Lcfi1:
; AVX2-NEXT: .cfi_def_cfa_offset 24
; AVX2-NEXT: pushq %r14
-; AVX2-NEXT: .Ltmp2:
+; AVX2-NEXT: .Lcfi2:
; AVX2-NEXT: .cfi_def_cfa_offset 32
; AVX2-NEXT: pushq %r13
-; AVX2-NEXT: .Ltmp3:
+; AVX2-NEXT: .Lcfi3:
; AVX2-NEXT: .cfi_def_cfa_offset 40
; AVX2-NEXT: pushq %r12
-; AVX2-NEXT: .Ltmp4:
+; AVX2-NEXT: .Lcfi4:
; AVX2-NEXT: .cfi_def_cfa_offset 48
; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: .Ltmp5:
+; AVX2-NEXT: .Lcfi5:
; AVX2-NEXT: .cfi_def_cfa_offset 56
-; AVX2-NEXT: .Ltmp6:
+; AVX2-NEXT: .Lcfi6:
; AVX2-NEXT: .cfi_offset %rbx, -56
-; AVX2-NEXT: .Ltmp7:
+; AVX2-NEXT: .Lcfi7:
; AVX2-NEXT: .cfi_offset %r12, -48
-; AVX2-NEXT: .Ltmp8:
+; AVX2-NEXT: .Lcfi8:
; AVX2-NEXT: .cfi_offset %r13, -40
-; AVX2-NEXT: .Ltmp9:
+; AVX2-NEXT: .Lcfi9:
; AVX2-NEXT: .cfi_offset %r14, -32
-; AVX2-NEXT: .Ltmp10:
+; AVX2-NEXT: .Lcfi10:
; AVX2-NEXT: .cfi_offset %r15, -24
-; AVX2-NEXT: .Ltmp11:
+; AVX2-NEXT: .Lcfi11:
; AVX2-NEXT: .cfi_offset %rbp, -16
; AVX2-NEXT: movswq (%rdi), %rax
; AVX2-NEXT: movq %rax, %rcx
@@ -4772,7 +4772,7 @@ define i32 @sext_2i8_to_i32(<16 x i8> %A
; X32-SSE41-LABEL: sext_2i8_to_i32:
; X32-SSE41: # BB#0: # %entry
; X32-SSE41-NEXT: pushl %eax
-; X32-SSE41-NEXT: .Ltmp0:
+; X32-SSE41-NEXT: .Lcfi0:
; X32-SSE41-NEXT: .cfi_def_cfa_offset 8
; X32-SSE41-NEXT: pmovsxbw %xmm0, %xmm0
; X32-SSE41-NEXT: movd %xmm0, %eax
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-mmx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-mmx.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-mmx.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-mmx.ll Wed Nov 30 17:48:26 2016
@@ -32,12 +32,12 @@ define void @test1() {
; X32-LABEL: test1:
; X32: ## BB#0: ## %entry
; X32-NEXT: pushl %edi
-; X32-NEXT: Ltmp0:
+; X32-NEXT: Lcfi0:
; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: subl $16, %esp
-; X32-NEXT: Ltmp1:
+; X32-NEXT: Lcfi1:
; X32-NEXT: .cfi_def_cfa_offset 24
-; X32-NEXT: Ltmp2:
+; X32-NEXT: Lcfi2:
; X32-NEXT: .cfi_offset %edi, -8
; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movlps %xmm0, (%esp)
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll Wed Nov 30 17:48:26 2016
@@ -393,12 +393,12 @@ define i64 @shuf64i1_zero(i64 %a) {
; AVX512F-LABEL: shuf64i1_zero:
; AVX512F: # BB#0:
; AVX512F-NEXT: pushq %rbp
-; AVX512F-NEXT: .Ltmp0:
+; AVX512F-NEXT: .Lcfi0:
; AVX512F-NEXT: .cfi_def_cfa_offset 16
-; AVX512F-NEXT: .Ltmp1:
+; AVX512F-NEXT: .Lcfi1:
; AVX512F-NEXT: .cfi_offset %rbp, -16
; AVX512F-NEXT: movq %rsp, %rbp
-; AVX512F-NEXT: .Ltmp2:
+; AVX512F-NEXT: .Lcfi2:
; AVX512F-NEXT: .cfi_def_cfa_register %rbp
; AVX512F-NEXT: andq $-32, %rsp
; AVX512F-NEXT: subq $96, %rsp
Modified: llvm/trunk/test/CodeGen/X86/win-cleanuppad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win-cleanuppad.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/win-cleanuppad.ll (original)
+++ llvm/trunk/test/CodeGen/X86/win-cleanuppad.ll Wed Nov 30 17:48:26 2016
@@ -129,18 +129,18 @@ cleanup.outer:
; X64-LABEL: nested_cleanup:
; X64: .Lfunc_begin1:
-; X64: .Ltmp13:
+; X64: .Ltmp2:
; X64: movl $1, %ecx
; X64: callq f
-; X64: .Ltmp15:
+; X64: .Ltmp4:
; X64: movl $2, %ecx
; X64: callq f
-; X64: .Ltmp16:
+; X64: .Ltmp5:
; X64: callq "??1Dtor@@QAE at XZ"
-; X64: .Ltmp17:
+; X64: .Ltmp6:
; X64: movl $3, %ecx
; X64: callq f
-; X64: .Ltmp18:
+; X64: .Ltmp7:
; X64: "?dtor$[[cleanup_inner:[0-9]+]]@?0?nested_cleanup at 4HA":
; X64: LBB1_[[cleanup_inner]]: # %cleanup.inner{{$}}
@@ -185,13 +185,13 @@ cleanup.outer:
; X64: $ip2state$nested_cleanup:
; X64-NEXT: .long .Lfunc_begin1 at IMGREL
; X64-NEXT: .long -1
-; X64-NEXT: .long .Ltmp13 at IMGREL
+; X64-NEXT: .long .Ltmp2 at IMGREL
; X64-NEXT: .long 0
-; X64-NEXT: .long .Ltmp15 at IMGREL
+; X64-NEXT: .long .Ltmp4 at IMGREL
; X64-NEXT: .long 1
-; X64-NEXT: .long .Ltmp17 at IMGREL
+; X64-NEXT: .long .Ltmp6 at IMGREL
; X64-NEXT: .long 0
-; X64-NEXT: .long .Ltmp18 at IMGREL+1
+; X64-NEXT: .long .Ltmp7 at IMGREL+1
; X64-NEXT: .long -1
attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
Modified: llvm/trunk/test/CodeGen/X86/win32-pic-jumptable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win32-pic-jumptable.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/win32-pic-jumptable.ll (original)
+++ llvm/trunk/test/CodeGen/X86/win32-pic-jumptable.ll Wed Nov 30 17:48:26 2016
@@ -1,11 +1,11 @@
; RUN: llc < %s -relocation-model=pic | FileCheck %s
; CHECK: calll L0$pb
-; CHECK-NEXT: Ltmp{{[0-9]+}}:
+; CHECK-NEXT: Lcfi{{[0-9]+}}:
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: L0$pb:
; CHECK-NEXT: popl %eax
-; CHECK-NEXT: Ltmp{{[0-9]+}}:
+; CHECK-NEXT: Lcfi{{[0-9]+}}:
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: addl LJTI0_0(,%ecx,4), %eax
; CHECK-NEXT: jmpl *%eax
Modified: llvm/trunk/test/CodeGen/XCore/epilogue_prologue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/epilogue_prologue.ll?rev=288290&r1=288289&r2=288290&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/epilogue_prologue.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/epilogue_prologue.ll Wed Nov 30 17:48:26 2016
@@ -62,18 +62,18 @@ entry:
; FP + large frame: spill FP+SR = entsp 2 + 100000
; CHECKFP-LABEL: f4
; CHECKFP: entsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 15, 0
; CHECKFP-NEXT: extsp 34467
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
; CHECKFP-NEXT: stw r10, sp[1]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 10, -400004
; CHECKFP-NEXT: ldaw r10, sp[0]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_register 10
; CHECKFP-NEXT: set sp, r10
; CHECKFP-NEXT: ldw r10, sp[1]
@@ -83,12 +83,12 @@ entry:
; !FP + large frame: spill SR+SR = entsp 2 + 100000
; CHECK-LABEL: f4
; CHECK: entsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 262140
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_offset 15, 0
; CHECK-NEXT: extsp 34467
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 400008
; CHECK-NEXT: ldaw sp, sp[65535]
; CHECK-NEXT: retsp 34467
@@ -109,28 +109,28 @@ entry:
; CHECKFP-NEXT: .text
; CHECKFP-LABEL: f6
; CHECKFP: entsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 15, 0
; CHECKFP-NEXT: extsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 524280
; CHECKFP-NEXT: extsp 65535
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 786420
; CHECKFP-NEXT: extsp 3398
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_offset 800012
; CHECKFP-NEXT: stw r10, sp[1]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 10, -800008
; CHECKFP-NEXT: ldaw r10, sp[0]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_def_cfa_register 10
; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1]
-; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
+; CHECKFP-NEXT: .Lcfi{{[0-9]+}}
; CHECKFP-NEXT: .cfi_offset 4, -4
; CHECKFP-NEXT: mov [[REG]], r0
; CHECKFP-NEXT: extsp 1
@@ -162,23 +162,23 @@ entry:
; CHECK-NEXT: .text
; CHECK-LABEL: f6
; CHECK: entsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 262140
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_offset 15, 0
; CHECK-NEXT: extsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 524280
; CHECK-NEXT: extsp 65535
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 786420
; CHECK-NEXT: extsp 3399
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_def_cfa_offset 800016
; CHECK-NEXT: ldaw r1, sp[0]
; CHECK-NEXT: ldw r2, cp[.LCPI[[CNST0]]]
; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2]
-; CHECK-NEXT: .Ltmp{{[0-9]+}}
+; CHECK-NEXT: .Lcfi{{[0-9]+}}
; CHECK-NEXT: .cfi_offset 4, -4
; CHECK-NEXT: mov [[REG]], r0
; CHECK-NEXT: ldaw r0, sp[3]
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