[llvm] r288262 - AMDGPU: Move mir tests into mir test directory
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 10:50:26 PST 2016
Author: arsenm
Date: Wed Nov 30 12:50:26 2016
New Revision: 288262
URL: http://llvm.org/viewvc/llvm-project?rev=288262&view=rev
Log:
AMDGPU: Move mir tests into mir test directory
Added:
llvm/trunk/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir
- copied, changed from r288259, llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir
- copied, changed from r288259, llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/liveness.mir
- copied, changed from r288259, llvm/trunk/test/CodeGen/AMDGPU/liveness.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir
- copied, changed from r288259, llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir
- copied, changed from r288259, llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir
Removed:
llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
llvm/trunk/test/CodeGen/AMDGPU/liveness.mir
llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir
llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir
Removed: llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir?rev=288261&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir (removed)
@@ -1,75 +0,0 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
-# Check that %11 and %20 have been coalesced.
-# CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG:[0-9]+]]
-# CHECK: IMAGE_SAMPLE_C_D_O_V1_V16 %[[REG]]
-
----
-name: main
-alignment: 0
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: vgpr_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: sreg_256 }
- - { id: 4, class: sreg_128 }
- - { id: 5, class: sreg_256 }
- - { id: 6, class: sreg_128 }
- - { id: 7, class: sreg_512 }
- - { id: 9, class: vreg_512 }
- - { id: 11, class: vreg_512 }
- - { id: 18, class: vgpr_32 }
- - { id: 20, class: vreg_512 }
- - { id: 27, class: vgpr_32 }
-liveins:
- - { reg: '%sgpr2_sgpr3', virtual-reg: '%0' }
- - { reg: '%vgpr2', virtual-reg: '%1' }
- - { reg: '%vgpr3', virtual-reg: '%2' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
-body: |
- bb.0:
- liveins: %sgpr2_sgpr3, %vgpr2, %vgpr3
-
- %0 = COPY %sgpr2_sgpr3
- %1 = COPY %vgpr2
- %2 = COPY %vgpr3
- %3 = S_LOAD_DWORDX8_IMM %0, 0, 0
- %4 = S_LOAD_DWORDX4_IMM %0, 12, 0
- %5 = S_LOAD_DWORDX8_IMM %0, 16, 0
- %6 = S_LOAD_DWORDX4_IMM %0, 28, 0
- undef %7.sub0 = S_MOV_B32 212739
- %20 = COPY %7
- %11 = COPY %20
- %11.sub1 = COPY %1
- %11.sub2 = COPY %1
- %11.sub3 = COPY %1
- %11.sub4 = COPY %1
- %11.sub5 = COPY %1
- %11.sub6 = COPY %1
- %11.sub7 = COPY %1
- %11.sub8 = COPY %1
- dead %18 = IMAGE_SAMPLE_C_D_O_V1_V16 %11, %3, %4, 1, 0, 0, 0, 0, 0, 0, -1, implicit %exec
- %20.sub1 = COPY %2
- %20.sub2 = COPY %2
- %20.sub3 = COPY %2
- %20.sub4 = COPY %2
- %20.sub5 = COPY %2
- %20.sub6 = COPY %2
- %20.sub7 = COPY %2
- %20.sub8 = COPY %2
- dead %27 = IMAGE_SAMPLE_C_D_O_V1_V16 %20, %5, %6, 1, 0, 0, 0, 0, 0, 0, -1, implicit %exec
-
-...
Removed: llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir?rev=288261&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir (removed)
@@ -1,419 +0,0 @@
-# RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
---- |
- define void @test0() { ret void }
- define void @test1() { ret void }
- define void @test2() { ret void }
- define void @test3() { ret void }
- define void @test4() { ret void }
- define void @test5() { ret void }
- define void @loop0() { ret void }
- define void @loop1() { ret void }
- define void @loop2() { ret void }
-...
----
-# Combined use/def transfer check, the basics.
-# CHECK-LABEL: name: test0
-# CHECK: S_NOP 0, implicit-def %0
-# CHECK: S_NOP 0, implicit-def %1
-# CHECK: S_NOP 0, implicit-def dead %2
-# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %3.sub0
-# CHECK: S_NOP 0, implicit %3.sub1
-# CHECK: S_NOP 0, implicit undef %3.sub2
-# CHECK: %4 = COPY %3.sub0_sub1
-# CHECK: %5 = COPY undef %3.sub2_sub3
-# CHECK: S_NOP 0, implicit %4.sub0
-# CHECK: S_NOP 0, implicit %4.sub1
-# CHECK: S_NOP 0, implicit undef %5.sub0
-name: test0
-registers:
- - { id: 0, class: sreg_32_xm0 }
- - { id: 1, class: sreg_32_xm0 }
- - { id: 2, class: sreg_32_xm0 }
- - { id: 3, class: sreg_128 }
- - { id: 4, class: sreg_64 }
- - { id: 5, class: sreg_64 }
-body: |
- bb.0:
- S_NOP 0, implicit-def %0
- S_NOP 0, implicit-def %1
- S_NOP 0, implicit-def %2
- %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
- S_NOP 0, implicit %3.sub0
- S_NOP 0, implicit %3.sub1
- S_NOP 0, implicit %3.sub2
- %4 = COPY %3.sub0_sub1
- %5 = COPY %3.sub2_sub3
- S_NOP 0, implicit %4.sub0
- S_NOP 0, implicit %4.sub1
- S_NOP 0, implicit %5.sub0
-...
----
-# Check defined lanes transfer; Includes checking for some special cases like
-# undef operands or IMPLICIT_DEF definitions.
-# CHECK-LABEL: name: test1
-# CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
-# CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
-# CHECK: %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %1.sub0
-# CHECK: S_NOP 0, implicit undef %1.sub1
-# CHECK: S_NOP 0, implicit %1.sub2
-# CHECK: S_NOP 0, implicit %1.sub3
-# CHECK: S_NOP 0, implicit %2.sub0
-# CHECK: S_NOP 0, implicit undef %2.sub1
-
-# CHECK: %3 = IMPLICIT_DEF
-# CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit undef %4.sub0
-# CHECK: S_NOP 0, implicit undef %4.sub1
-# CHECK: S_NOP 0, implicit %4.sub2
-# CHECK: S_NOP 0, implicit undef %4.sub3
-
-# CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}}
-# CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}}
-# CHECK: %7 = EXTRACT_SUBREG %5, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %5
-# CHECK: S_NOP 0, implicit %6
-# CHECK: S_NOP 0, implicit undef %7
-
-# CHECK: %8 = IMPLICIT_DEF
-# CHECK: %9 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit undef %9
-
-# CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit undef %10
-name: test1
-registers:
- - { id: 0, class: sreg_128 }
- - { id: 1, class: sreg_128 }
- - { id: 2, class: sreg_64 }
- - { id: 3, class: sreg_32_xm0 }
- - { id: 4, class: sreg_128 }
- - { id: 5, class: sreg_64 }
- - { id: 6, class: sreg_32_xm0 }
- - { id: 7, class: sreg_32_xm0 }
- - { id: 8, class: sreg_64 }
- - { id: 9, class: sreg_32_xm0 }
- - { id: 10, class: sreg_128 }
-body: |
- bb.0:
- %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
- %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
- %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0
- S_NOP 0, implicit %1.sub0
- S_NOP 0, implicit %1.sub1
- S_NOP 0, implicit %1.sub2
- S_NOP 0, implicit %1.sub3
- S_NOP 0, implicit %2.sub0
- S_NOP 0, implicit %2.sub1
-
- %3 = IMPLICIT_DEF
- %4 = INSERT_SUBREG %0, %3, %subreg.sub0
- S_NOP 0, implicit %4.sub0
- S_NOP 0, implicit %4.sub1
- S_NOP 0, implicit %4.sub2
- S_NOP 0, implicit %4.sub3
-
- %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
- %6 = EXTRACT_SUBREG %5, %subreg.sub0
- %7 = EXTRACT_SUBREG %5, %subreg.sub1
- S_NOP 0, implicit %5
- S_NOP 0, implicit %6
- S_NOP 0, implicit %7
-
- %8 = IMPLICIT_DEF
- %9 = EXTRACT_SUBREG %8, %subreg.sub1
- S_NOP 0, implicit %9
-
- %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
- S_NOP 0, implicit %10
-...
----
-# Check used lanes transfer; Includes checking for some special cases like
-# undef operands.
-# CHECK-LABEL: name: test2
-# CHECK: S_NOP 0, implicit-def dead %0
-# CHECK: S_NOP 0, implicit-def %1
-# CHECK: S_NOP 0, implicit-def %2
-# CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %3.sub1
-# CHECK: S_NOP 0, implicit %3.sub3
-
-# CHECK: S_NOP 0, implicit-def %4
-# CHECK: S_NOP 0, implicit-def dead %5
-# CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %6
-
-# CHECK: S_NOP 0, implicit-def dead %7
-# CHECK: S_NOP 0, implicit-def %8
-# CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %9.sub2
-
-# CHECK: S_NOP 0, implicit-def %10
-# CHECK: S_NOP 0, implicit-def dead %11
-# CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %12.sub3
-
-# CHECK: S_NOP 0, implicit-def %13
-# CHECK: S_NOP 0, implicit-def dead %14
-# CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
-# CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %16.sub1
-
-name: test2
-registers:
- - { id: 0, class: sreg_32_xm0 }
- - { id: 1, class: sreg_32_xm0 }
- - { id: 2, class: sreg_64 }
- - { id: 3, class: sreg_128 }
- - { id: 4, class: sreg_32_xm0 }
- - { id: 5, class: sreg_32_xm0 }
- - { id: 6, class: sreg_64 }
- - { id: 7, class: sreg_128 }
- - { id: 8, class: sreg_64 }
- - { id: 9, class: sreg_128 }
- - { id: 10, class: sreg_128 }
- - { id: 11, class: sreg_64 }
- - { id: 12, class: sreg_128 }
- - { id: 13, class: sreg_64 }
- - { id: 14, class: sreg_64 }
- - { id: 15, class: sreg_128 }
- - { id: 16, class: sreg_64 }
-body: |
- bb.0:
- S_NOP 0, implicit-def %0
- S_NOP 0, implicit-def %1
- S_NOP 0, implicit-def %2
- %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
- S_NOP 0, implicit %3.sub1
- S_NOP 0, implicit %3.sub3
-
- S_NOP 0, implicit-def %4
- S_NOP 0, implicit-def %5
- %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
- S_NOP 0, implicit %6
-
- S_NOP 0, implicit-def %7
- S_NOP 0, implicit-def %8
- %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
- S_NOP 0, implicit %9.sub2
-
- S_NOP 0, implicit-def %10
- S_NOP 0, implicit-def %11
- %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
- S_NOP 0, implicit %12.sub3
-
- S_NOP 0, implicit-def %13
- S_NOP 0, implicit-def %14
- %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
- %16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
- S_NOP 0, implicit %16.sub1
-...
----
-# Check that copies to physregs use all lanes, copies from physregs define all
-# lanes. So we should not get a dead/undef flag here.
-# CHECK-LABEL: name: test3
-# CHECK: S_NOP 0, implicit-def %0
-# CHECK: %vcc = COPY %0
-# CHECK: %1 = COPY %vcc
-# CHECK: S_NOP 0, implicit %1
-name: test3
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_64 }
-body: |
- bb.0:
- S_NOP 0, implicit-def %0
- %vcc = COPY %0
-
- %1 = COPY %vcc
- S_NOP 0, implicit %1
-...
----
-# Check that implicit-def/kill do not count as def/uses.
-# CHECK-LABEL: name: test4
-# CHECK: S_NOP 0, implicit-def dead %0
-# CHECK: KILL undef %0
-# CHECK: %1 = IMPLICIT_DEF
-# CHECK: S_NOP 0, implicit undef %1
-name: test4
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_64 }
- - { id: 1, class: sreg_64 }
-body: |
- bb.0:
- S_NOP 0, implicit-def %0
- KILL %0
-
- %1 = IMPLICIT_DEF
- S_NOP 0, implicit %1
-...
----
-# Check that unused inputs are marked as undef, even if the vreg itself is
-# used.
-# CHECK-LABEL: name: test5
-# CHECK: S_NOP 0, implicit-def %0
-# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %1.sub1
-name: test5
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_32_xm0 }
- - { id: 1, class: sreg_64 }
-body: |
- bb.0:
- S_NOP 0, implicit-def %0
- %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
- S_NOP 0, implicit %1.sub1
-...
----
-# Check "optimistic" dataflow fixpoint in phi-loops.
-# CHECK-LABEL: name: loop0
-# CHECK: bb.0:
-# CHECK: S_NOP 0, implicit-def %0
-# CHECK: S_NOP 0, implicit-def dead %1
-# CHECK: S_NOP 0, implicit-def dead %2
-# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
-
-# CHECK: bb.1:
-# CHECK: %4 = PHI %3, %bb.0, %5, %bb.1
-
-# CHECK: bb.2:
-# CHECK: S_NOP 0, implicit %4.sub0
-# CHECK: S_NOP 0, implicit undef %4.sub3
-name: loop0
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_32_xm0 }
- - { id: 1, class: sreg_32_xm0 }
- - { id: 2, class: sreg_32_xm0 }
- - { id: 3, class: sreg_128 }
- - { id: 4, class: sreg_128 }
- - { id: 5, class: sreg_128 }
-body: |
- bb.0:
- successors: %bb.1
- S_NOP 0, implicit-def %0
- S_NOP 0, implicit-def %1
- S_NOP 0, implicit-def %2
- %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
- S_BRANCH %bb.1
-
- bb.1:
- successors: %bb.1, %bb.2
- %4 = PHI %3, %bb.0, %5, %bb.1
-
- ; let's swiffle some lanes around for fun...
- %5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3
-
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
- S_BRANCH %bb.2
-
- bb.2:
- S_NOP 0, implicit %4.sub0
- S_NOP 0, implicit %4.sub3
-...
----
-# Check a loop that needs to be traversed multiple times to reach the fixpoint
-# for the used lanes. The example reads sub3 lane at the end, however with each
-# loop iteration we should get 1 more lane marked as we cycles the sublanes
-# along. Sublanes sub0, sub1 and sub3 are rotate in the loop so only sub2
-# should be dead.
-# CHECK-LABEL: name: loop1
-# CHECK: bb.0:
-# CHECK: S_NOP 0, implicit-def %0
-# CHECK: S_NOP 0, implicit-def %1
-# CHECK: S_NOP 0, implicit-def dead %2
-# CHECK: S_NOP 0, implicit-def %3
-# CHECK: %4 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
-
-# CHECK: bb.1:
-# CHECK: %5 = PHI %4, %bb.0, %6, %bb.1
-
-# CHECK: %6 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
-
-# CHECK: bb.2:
-# CHECK: S_NOP 0, implicit %6.sub3
-name: loop1
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_32_xm0 }
- - { id: 1, class: sreg_32_xm0 }
- - { id: 2, class: sreg_32_xm0 }
- - { id: 3, class: sreg_32_xm0 }
- - { id: 4, class: sreg_128 }
- - { id: 5, class: sreg_128 }
- - { id: 6, class: sreg_128 }
-body: |
- bb.0:
- successors: %bb.1
- S_NOP 0, implicit-def %0
- S_NOP 0, implicit-def %1
- S_NOP 0, implicit-def dead %2
- S_NOP 0, implicit-def %3
- %4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
- S_BRANCH %bb.1
-
- bb.1:
- successors: %bb.1, %bb.2
- %5 = PHI %4, %bb.0, %6, %bb.1
-
- ; rotate lanes, but skip sub2 lane...
- %6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
-
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
- S_BRANCH %bb.2
-
- bb.2:
- S_NOP 0, implicit %6.sub3
-...
----
-# Similar to loop1 test, but check for fixpoint of defined lanes.
-# Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
-# CHECK-LABEL: name: loop2
-# CHECK: bb.0:
-# CHECK: S_NOP 0, implicit-def %0
-# CHECK: %1 = REG_SEQUENCE %0, {{[0-9]+}}
-
-# CHECK: bb.1:
-# CHECK: %2 = PHI %1, %bb.0, %3, %bb.1
-
-# CHECK: %3 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
-
-# CHECK: bb.2:
-# CHECK: S_NOP 0, implicit %2.sub0
-# CHECK: S_NOP 0, implicit undef %2.sub1
-# CHECK: S_NOP 0, implicit %2.sub2
-# CHECK: S_NOP 0, implicit %2.sub3
-name: loop2
-tracksRegLiveness: true
-registers:
- - { id: 0, class: sreg_32_xm0 }
- - { id: 1, class: sreg_128 }
- - { id: 2, class: sreg_128 }
- - { id: 3, class: sreg_128 }
-body: |
- bb.0:
- successors: %bb.1
- S_NOP 0, implicit-def %0
- %1 = REG_SEQUENCE %0, %subreg.sub0
- S_BRANCH %bb.1
-
- bb.1:
- successors: %bb.1, %bb.2
- %2 = PHI %1, %bb.0, %3, %bb.1
-
- ; rotate subreg lanes, skipping sub1
- %3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
-
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
- S_BRANCH %bb.2
-
- bb.2:
- S_NOP 0, implicit %2.sub0
- S_NOP 0, implicit undef %2.sub1
- S_NOP 0, implicit %2.sub2
- S_NOP 0, implicit %2.sub3
-...
Removed: llvm/trunk/test/CodeGen/AMDGPU/liveness.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/liveness.mir?rev=288261&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/liveness.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/liveness.mir (removed)
@@ -1,32 +0,0 @@
-# RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s
-# REQUIRES: asserts
-# We currently maintain a main liveness range which operates like a superset of
-# all subregister liveranges. We may need to create additional SSA values at
-# merge point in this main liverange even though none of the subregister
-# liveranges needed it.
-#
-# Should see three distinct value numbers:
-# CHECK: %vreg0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}
---- |
- define void @test0() { ret void }
-...
----
-name: test0
-registers:
- - { id: 0, class: sreg_64 }
-body: |
- bb.0:
- successors: %bb.1, %bb.2
- S_NOP 0, implicit-def undef %0.sub0
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
- S_BRANCH %bb.2
-
- bb.1:
- successors: %bb.2
- S_NOP 0, implicit-def %0.sub1
- S_NOP 0, implicit %0.sub1
- S_BRANCH %bb.2
-
- bb.2:
- S_NOP 0, implicit %0.sub0
-...
Removed: llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir?rev=288261&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir (removed)
@@ -1,70 +0,0 @@
-# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck %s
---- |
- define void @test0() { ret void }
- define void @test1() { ret void }
-...
----
-# In the test below we have two independent def+use pairs of subregister1 which
-# can be moved to a new virtual register. The third def of sub1 however is used
-# in combination with sub0 and needs to stay with the original vreg.
-# CHECK-LABEL: name: test0
-# CHECK: S_NOP 0, implicit-def undef %0.sub0
-# CHECK: S_NOP 0, implicit-def undef %2.sub1
-# CHECK: S_NOP 0, implicit %2.sub1
-# CHECK: S_NOP 0, implicit-def undef %1.sub1
-# CHECK: S_NOP 0, implicit %1.sub1
-# CHECK: S_NOP 0, implicit-def %0.sub1
-# CHECK: S_NOP 0, implicit %0
-name: test0
-registers:
- - { id: 0, class: sreg_128 }
-body: |
- bb.0:
- S_NOP 0, implicit-def undef %0.sub0
- S_NOP 0, implicit-def %0.sub1
- S_NOP 0, implicit %0.sub1
- S_NOP 0, implicit-def %0.sub1
- S_NOP 0, implicit %0.sub1
- S_NOP 0, implicit-def %0.sub1
- S_NOP 0, implicit %0
-...
----
-# Test for a bug where we would incorrectly query liveness at the instruction
-# index in rewriteOperands(). This should pass the verifier afterwards.
-# CHECK-LABEL: test1
-# CHECK: bb.0
-# CHECK: S_NOP 0, implicit-def undef %2.sub2
-# CHECK: bb.1
-# CHECK: S_NOP 0, implicit-def %2.sub1
-# CHECK-NEXT: S_NOP 0, implicit-def %2.sub3
-# CHECK-NEXT: S_NOP 0, implicit %2
-# CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub0
-# CHECK-NEXT: S_NOP 0, implicit %2.sub1
-# CHECK-NEXT: S_NOP 0, implicit %0.sub0
-# CHECK: bb.2
-# CHECK: S_NOP 0, implicit %2.sub
-name: test1
-registers:
- - { id: 0, class: sreg_128 }
- - { id: 1, class: sreg_128 }
-body: |
- bb.0:
- successors: %bb.1, %bb.2
- S_NOP 0, implicit-def undef %0.sub2
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
- S_BRANCH %bb.2
-
- bb.1:
- S_NOP 0, implicit-def %0.sub1
- S_NOP 0, implicit-def %0.sub3
- %1 = COPY %0
- S_NOP 0, implicit %1
-
- S_NOP 0, implicit-def %1.sub0
- S_NOP 0, implicit %1.sub1
- S_NOP 0, implicit %1.sub0
-
- bb.2:
- S_NOP 0, implicit %0.sub2
-
-...
Removed: llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir?rev=288261&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir (removed)
@@ -1,51 +0,0 @@
-# RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
-# REQUIRES: asserts
-
-# CHECK: INTERVALS
-# CHECK: vreg0
-# CHECK-LABEL: Machine code for function test0:
-
-# CHECK: INTERVALS
-# CHECK: vreg0
-# CHECK-LABEL: Machine code for function test1:
-
---- |
- define void @test0() { ret void }
- define void @test1() { ret void }
-...
----
-name: test0
-registers:
- - { id: 0, class: sreg_64 }
-body: |
- bb.0:
- S_NOP 0, implicit-def %0
- S_NOP 0, implicit %0
-
- S_NOP 0, implicit-def undef %0.sub0
- S_NOP 0, implicit %0
-...
----
-name: test1
-registers:
- - { id: 0, class: sreg_64 }
-body: |
- bb.0:
- successors: %bb.1, %bb.2
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
- S_BRANCH %bb.2
-
- bb.1:
- successors: %bb.3
- S_NOP 0, implicit-def undef %0.sub0
- S_BRANCH %bb.3
-
- bb.2:
- successors: %bb.3
- S_NOP 0, implicit-def %0
- S_BRANCH %bb.3
-
- bb.3:
- S_NOP 0
- S_NOP 0, implicit %0
-...
Copied: llvm/trunk/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir (from r288259, llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir?p2=llvm/trunk/test/CodeGen/MIR/AMDGPU/coalescer-subreg-join.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/coalescer-subreg-join.mir&r1=288259&r2=288262&rev=288262&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir (from r288259, llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir?p2=llvm/trunk/test/CodeGen/MIR/AMDGPU/detect-dead-lanes.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir&r1=288259&r2=288262&rev=288262&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/MIR/AMDGPU/liveness.mir (from r288259, llvm/trunk/test/CodeGen/AMDGPU/liveness.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/liveness.mir?p2=llvm/trunk/test/CodeGen/MIR/AMDGPU/liveness.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/liveness.mir&r1=288259&r2=288262&rev=288262&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir (from r288259, llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir?p2=llvm/trunk/test/CodeGen/MIR/AMDGPU/rename-independent-subregs.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir&r1=288259&r2=288262&rev=288262&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir (from r288259, llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir?p2=llvm/trunk/test/CodeGen/MIR/AMDGPU/subreg-intervals.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir&r1=288259&r2=288262&rev=288262&view=diff
==============================================================================
(empty)
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