[llvm] r288206 - [AArch64] allow and-not-compare transform to form 'bics'
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 14:28:58 PST 2016
Author: spatel
Date: Tue Nov 29 16:28:58 2016
New Revision: 288206
URL: http://llvm.org/viewvc/llvm-project?rev=288206&view=rev
Log:
[AArch64] allow and-not-compare transform to form 'bics'
This target hook was added with D19087:
https://reviews.llvm.org/D19087
Differential Revision: https://reviews.llvm.org/D27221
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
llvm/trunk/test/CodeGen/AArch64/bics.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=288206&r1=288205&r2=288206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Tue Nov 29 16:28:58 2016
@@ -412,6 +412,11 @@ public:
return true;
}
+ bool hasAndNotCompare(SDValue) const override {
+ // 'bics'
+ return true;
+ }
+
bool hasBitPreservingFPLogic(EVT VT) const override {
// FIXME: Is this always true? It should be true for vectors at least.
return VT == MVT::f32 || VT == MVT::f64;
Modified: llvm/trunk/test/CodeGen/AArch64/bics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bics.ll?rev=288206&r1=288205&r2=288206&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/bics.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/bics.ll Tue Nov 29 16:28:58 2016
@@ -13,13 +13,10 @@ define i1 @andn_cmp(i32 %x, i32 %y) {
ret i1 %cmp
}
-; FIXME: Recognize a disguised bics.
-
define i1 @and_cmp(i32 %x, i32 %y) {
; CHECK-LABEL: and_cmp:
; CHECK: // BB#0:
-; CHECK-NEXT: and w8, w0, w1
-; CHECK-NEXT: cmp w8, w1
+; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
;
@@ -32,8 +29,7 @@ define i1 @and_cmp_const(i32 %x) {
; CHECK-LABEL: and_cmp_const:
; CHECK: // BB#0:
; CHECK-NEXT: mov w8, #43
-; CHECK-NEXT: and w8, w0, w8
-; CHECK-NEXT: cmp w8, #43
+; CHECK-NEXT: bics wzr, w8, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
;
More information about the llvm-commits
mailing list