[PATCH] D27148: Regcall - Adding support for mask types

[Amjad Aboud via Phabricator via llvm-commits]

aaboud added a comment.

Please, create the patch using the following command:
svn diff --diff-cmd=diff -x -U999999



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:2103
 
-  if (ValVT == MVT::v64i1 && ValLoc == MVT::i64) {
+  if (ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) {
+    // Two stage lowering might be required
----------------
How about this refactoring?

```

 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
     (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
    // Two stage lowering might be required
    // bitcast:   v8i1 -> i8 / v16i1 -> i16
    // anyextend: i8   -> i32 / i16   -> i32
    EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
    SDValue ValToCopy = DAG.getBitcast(TempValLoc, ValArg);
    if (ValLoc == MVT::i32)
      ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
    return ValToCopy;
  } else if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
             (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
    // One stage lowering is required
    // bitcast:   v32i1 -> i32 / v64i1 -> i64
    return DAG.getBitcast(ValLoc, ValArg);
  } else

```


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:2461
 
-  // Currently not referenced - will be used in other mask lowering
-  (void)Dl;
-
-  // In the case of v64i1 no special handling is required due to two reasons:
-  // In 32 bit machine, this case is handled by getv64i1Argument
-  // In 64 bit machine, There is no need to truncate the value only bitcast
-  if (ValVT == MVT::v64i1 && ValLoc == MVT::i32) {
-    llvm_unreachable("Expecting only i64 locations");
+  if (ValVT == MVT::v8i1) {
+    ValReturned = DAG.getNode(ISD::TRUNCATE, Dl, MVT::i8, ValReturned);
----------------
Run clang-format on these changes.


Repository:
  rL LLVM

https://reviews.llvm.org/D27148