[PATCH] D25914: Redo store splitting in CodeGenPrepare

[David Majnemer via Phabricator via llvm-commits]

majnemer added inline comments.


================
Comment at: lib/CodeGen/CodeGenPrepare.cpp:5300-5301
+                                const TargetLowering &TLI) {
+  unsigned HalfValBitSize =
+      DL.getTypeSizeInBits(SI.getValueOperand()->getType()) / 2;
+
----------------
wmi wrote:
> majnemer wrote:
> > This looks wrong. Shouldn't it be `getTypeStoreSizeInBits` instead of `getTypeSizeInBits`?
> They are the same here because the type of the store value must have power of 2 size if it is a merged store. But you remind me to add some testcases: @int31_float_pair, @int15_float_pair, @int7_float_pair added in the testcase. 
But aren't i1, i2 and i4 powers of two?

If we stored an i1, `HalfValBitSize` would be zero which sounds problematic.


Repository:
  rL LLVM

https://reviews.llvm.org/D25914