[llvm] r288031 - [SystemZ] Support execution hint instructions
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 28 06:01:51 PST 2016
Author: uweigand
Date: Mon Nov 28 08:01:51 2016
New Revision: 288031
URL: http://llvm.org/viewvc/llvm-project?rev=288031&view=rev
Log:
[SystemZ] Support execution hint instructions
This adds assembler support for the instructions provided by the
execution-hint facility (NIAI and BP(R)P). This required adding
support for the new relocation types for 12-bit and 24-bit PC-
relative offsets used by the BP(R)P instructions.
Added:
llvm/trunk/test/MC/SystemZ/fixups-zEC12.s
Modified:
llvm/trunk/include/llvm/Support/ELFRelocs/SystemZ.def
llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
llvm/trunk/lib/Target/SystemZ/SystemZFeatures.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s
llvm/trunk/test/MC/SystemZ/insn-good-zEC12.s
Modified: llvm/trunk/include/llvm/Support/ELFRelocs/SystemZ.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELFRelocs/SystemZ.def?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ELFRelocs/SystemZ.def (original)
+++ llvm/trunk/include/llvm/Support/ELFRelocs/SystemZ.def Mon Nov 28 08:01:51 2016
@@ -65,3 +65,7 @@ ELF_RELOC(R_390_GOT20, 58)
ELF_RELOC(R_390_GOTPLT20, 59)
ELF_RELOC(R_390_TLS_GOTIE20, 60)
ELF_RELOC(R_390_IRELATIVE, 61)
+ELF_RELOC(R_390_PC12DBL, 62)
+ELF_RELOC(R_390_PLT12DBL, 63)
+ELF_RELOC(R_390_PC24DBL, 64)
+ELF_RELOC(R_390_PLT24DBL, 65)
Modified: llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp Mon Nov 28 08:01:51 2016
@@ -484,9 +484,15 @@ public:
OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
}
+ OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
+ return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
+ }
OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
}
+ OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
+ return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
+ }
OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
}
Modified: llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp Mon Nov 28 08:01:51 2016
@@ -247,12 +247,24 @@ static DecodeStatus decodePCDBLOperand(M
return MCDisassembler::Success;
}
+static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
+}
+
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
}
+static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
+}
+
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address,
const void *Decoder) {
Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp Mon Nov 28 08:01:51 2016
@@ -25,7 +25,9 @@ static uint64_t extractBitsForFixup(MCFi
return Value;
switch (unsigned(Kind)) {
+ case SystemZ::FK_390_PC12DBL:
case SystemZ::FK_390_PC16DBL:
+ case SystemZ::FK_390_PC24DBL:
case SystemZ::FK_390_PC32DBL:
return (int64_t)Value / 2;
@@ -72,7 +74,9 @@ public:
const MCFixupKindInfo &
SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
+ { "FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "FK_390_TLS_CALL", 0, 0, 0 }
};
Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp Mon Nov 28 08:01:51 2016
@@ -113,6 +113,24 @@ private:
return getPCRelEncoding(MI, OpNum, Fixups,
SystemZ::FK_390_PC32DBL, 2, true);
}
+ uint64_t getPC12DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ return getPCRelEncoding(MI, OpNum, Fixups,
+ SystemZ::FK_390_PC12DBL, 1, false);
+ }
+ uint64_t getPC16DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ return getPCRelEncoding(MI, OpNum, Fixups,
+ SystemZ::FK_390_PC16DBL, 4, false);
+ }
+ uint64_t getPC24DBLBPPEncoding(const MCInst &MI, unsigned OpNum,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ return getPCRelEncoding(MI, OpNum, Fixups,
+ SystemZ::FK_390_PC24DBL, 3, false);
+ }
private:
uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h Mon Nov 28 08:01:51 2016
@@ -16,7 +16,9 @@ namespace llvm {
namespace SystemZ {
enum FixupKind {
// These correspond directly to R_390_* relocations.
- FK_390_PC16DBL = FirstTargetFixupKind,
+ FK_390_PC12DBL = FirstTargetFixupKind,
+ FK_390_PC16DBL,
+ FK_390_PC24DBL,
FK_390_PC32DBL,
FK_390_TLS_CALL,
Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp Mon Nov 28 08:01:51 2016
@@ -53,7 +53,9 @@ static unsigned getPCRelReloc(unsigned K
case FK_Data_2: return ELF::R_390_PC16;
case FK_Data_4: return ELF::R_390_PC32;
case FK_Data_8: return ELF::R_390_PC64;
+ case SystemZ::FK_390_PC12DBL: return ELF::R_390_PC12DBL;
case SystemZ::FK_390_PC16DBL: return ELF::R_390_PC16DBL;
+ case SystemZ::FK_390_PC24DBL: return ELF::R_390_PC24DBL;
case SystemZ::FK_390_PC32DBL: return ELF::R_390_PC32DBL;
}
llvm_unreachable("Unsupported PC-relative address");
@@ -100,7 +102,9 @@ static unsigned getTLSGDReloc(unsigned K
// Return the PLT relocation counterpart of MCFixupKind Kind.
static unsigned getPLTReloc(unsigned Kind) {
switch (Kind) {
+ case SystemZ::FK_390_PC12DBL: return ELF::R_390_PLT12DBL;
case SystemZ::FK_390_PC16DBL: return ELF::R_390_PLT16DBL;
+ case SystemZ::FK_390_PC24DBL: return ELF::R_390_PLT24DBL;
case SystemZ::FK_390_PC32DBL: return ELF::R_390_PLT32DBL;
}
llvm_unreachable("Unsupported absolute address");
Modified: llvm/trunk/lib/Target/SystemZ/SystemZFeatures.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFeatures.td?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZFeatures.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZFeatures.td Mon Nov 28 08:01:51 2016
@@ -84,6 +84,11 @@ def Arch9NewFeatures : SystemZFeatureLis
//
//===----------------------------------------------------------------------===//
+def FeatureExecutionHint : SystemZFeature<
+ "execution-hint", "ExecutionHint",
+ "Assume that the execution-hint facility is installed"
+>;
+
def FeatureLoadAndTrap : SystemZFeature<
"load-and-trap", "LoadAndTrap",
"Assume that the load-and-trap facility is installed"
@@ -105,6 +110,7 @@ def FeatureTransactionalExecution : Syst
>;
def Arch10NewFeatures : SystemZFeatureList<[
+ FeatureExecutionHint,
FeatureLoadAndTrap,
FeatureMiscellaneousExtensions,
FeatureProcessorAssist,
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Mon Nov 28 08:01:51 2016
@@ -177,6 +177,35 @@ class InstI<bits<8> op, dag outs, dag in
let Inst{7-0} = I1;
}
+class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<4, outs, ins, asmstr, pattern> {
+ field bits<32> Inst;
+ field bits<32> SoftFail = 0;
+
+ bits<4> I1;
+ bits<4> I2;
+
+ let Inst{31-16} = op;
+ let Inst{15-8} = 0;
+ let Inst{7-4} = I1;
+ let Inst{3-0} = I2;
+}
+
+class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<6, outs, ins, asmstr, pattern> {
+ field bits<48> Inst;
+ field bits<48> SoftFail = 0;
+
+ bits<4> M1;
+ bits<12> RI2;
+ bits<24> RI3;
+
+ let Inst{47-40} = op;
+ let Inst{39-36} = M1;
+ let Inst{35-24} = RI2;
+ let Inst{23-0} = RI3;
+}
+
class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
@@ -759,6 +788,22 @@ class InstSIY<bits<16> op, dag outs, dag
let Has20BitOffset = 1;
}
+class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<6, outs, ins, asmstr, pattern> {
+ field bits<48> Inst;
+ field bits<48> SoftFail = 0;
+
+ bits<4> M1;
+ bits<16> RI2;
+ bits<16> BD3;
+
+ let Inst{47-40} = op;
+ let Inst{39-36} = M1;
+ let Inst{35-32} = 0;
+ let Inst{31-16} = BD3;
+ let Inst{15-0} = RI2;
+}
+
class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
@@ -1605,6 +1650,9 @@ class ICV<string name>
// One 4-bit immediate operand and one address operand. The immediate
// operand is 1 for a load prefetch and 2 for a store prefetch.
//
+// BranchPreload:
+// One 4-bit immediate operand and two address operands.
+//
// The format determines which input operands are tied to output operands,
// and also determines the shape of any address operand.
//
@@ -2504,6 +2552,13 @@ class SideEffectBinaryRILPC<string mnemo
let AddedComplexity = 7;
}
+class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
+ Immediate imm1, Immediate imm2>
+ : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
+ mnemonic#"\t$I1, $I2", []> {
+ let hasSideEffects = 1;
+}
+
class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
SDPatternOperator operator, Immediate imm>
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
@@ -3620,6 +3675,16 @@ class PrefetchRILPC<string mnemonic, bit
let AddedComplexity = 7;
}
+class BranchPreloadSMI<string mnemonic, bits<8> opcode>
+ : InstSMI<opcode, (outs),
+ (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
+ mnemonic#"\t$M1, $RI2, $BD3", []>;
+
+class BranchPreloadMII<string mnemonic, bits<8> opcode>
+ : InstMII<opcode, (outs),
+ (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
+ mnemonic#"\t$M1, $RI2, $RI3", []>;
+
// A floating-point load-and test operation. Create both a normal unary
// operation and one that acts as a comparison against zero.
// Note that the comparison against zero operation is not available if we
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Mon Nov 28 08:01:51 2016
@@ -1382,12 +1382,21 @@ def TML : InstAlias<"tml\t$R, $I", (TMLL
def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>;
//===----------------------------------------------------------------------===//
-// Prefetch
+// Prefetch and execution hint
//===----------------------------------------------------------------------===//
def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
+let Predicates = [FeatureExecutionHint] in {
+ // Branch Prediction Preload
+ def BPP : BranchPreloadSMI<"bpp", 0xC7>;
+ def BPRP : BranchPreloadMII<"bprp", 0xC5>;
+
+ // Next Instruction Access Intent
+ def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>;
+}
+
//===----------------------------------------------------------------------===//
// Atomic operations
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperands.td Mon Nov 28 08:01:51 2016
@@ -460,7 +460,9 @@ def fpimmneg0 : PatLeaf<(fpimm), [{ retu
//===----------------------------------------------------------------------===//
// PC-relative asm operands.
+def PCRel12 : PCRelAsmOperand<"12">;
def PCRel16 : PCRelAsmOperand<"16">;
+def PCRel24 : PCRelAsmOperand<"24">;
def PCRel32 : PCRelAsmOperand<"32">;
def PCRelTLS16 : PCRelTLSAsmOperand<"16">;
def PCRelTLS32 : PCRelTLSAsmOperand<"32">;
@@ -476,6 +478,20 @@ def brtarget32 : PCRelOperand<OtherVT, P
let DecoderMethod = "decodePC32DBLBranchOperand";
}
+// Variants of brtarget for use with branch prediction preload.
+def brtarget12bpp : PCRelOperand<OtherVT, PCRel12> {
+ let EncoderMethod = "getPC12DBLBPPEncoding";
+ let DecoderMethod = "decodePC12DBLBranchOperand";
+}
+def brtarget16bpp : PCRelOperand<OtherVT, PCRel16> {
+ let EncoderMethod = "getPC16DBLBPPEncoding";
+ let DecoderMethod = "decodePC16DBLBranchOperand";
+}
+def brtarget24bpp : PCRelOperand<OtherVT, PCRel24> {
+ let EncoderMethod = "getPC24DBLBPPEncoding";
+ let DecoderMethod = "decodePC24DBLBranchOperand";
+}
+
// Variants of brtarget16/32 with an optional additional TLS symbol.
// These are used to annotate calls to __tls_get_offset.
def tlssym : Operand<i64> { }
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td Mon Nov 28 08:01:51 2016
@@ -517,10 +517,13 @@ def : InstRW<[FXb], (instregex "TMLH(64)
def : InstRW<[FXb], (instregex "TMLL(64)?$")>;
//===----------------------------------------------------------------------===//
-// Prefetch
+// Prefetch and execution hint
//===----------------------------------------------------------------------===//
def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
+def : InstRW<[FXb, Lat2], (instregex "BPP$")>;
+def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
+def : InstRW<[FXb], (instregex "NIAI$")>;
//===----------------------------------------------------------------------===//
// Atomic operations
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td Mon Nov 28 08:01:51 2016
@@ -487,10 +487,12 @@ def : InstRW<[FXU], (instregex "TMLH(64)
def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
//===----------------------------------------------------------------------===//
-// Prefetch
+// Prefetch and execution hint
//===----------------------------------------------------------------------===//
def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
+def : InstRW<[LSU], (instregex "BP(R)?P$")>;
+def : InstRW<[FXU], (instregex "NIAI$")>;
//===----------------------------------------------------------------------===//
// Atomic operations
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Mon Nov 28 08:01:51 2016
@@ -39,8 +39,9 @@ SystemZSubtarget::SystemZSubtarget(const
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
- HasLoadAndTrap(false), HasTransactionalExecution(false),
- HasProcessorAssist(false), HasVector(false), HasLoadStoreOnCond2(false),
+ HasExecutionHint(false), HasLoadAndTrap(false),
+ HasTransactionalExecution(false), HasProcessorAssist(false),
+ HasVector(false), HasLoadStoreOnCond2(false),
HasLoadAndZeroRightmostByte(false),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this), TSInfo(), FrameLowering() {}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Mon Nov 28 08:01:51 2016
@@ -42,6 +42,7 @@ protected:
bool HasFastSerialization;
bool HasInterlockedAccess1;
bool HasMiscellaneousExtensions;
+ bool HasExecutionHint;
bool HasLoadAndTrap;
bool HasTransactionalExecution;
bool HasProcessorAssist;
@@ -114,6 +115,9 @@ public:
return HasMiscellaneousExtensions;
}
+ // Return true if the target has the execution-hint facility.
+ bool hasExecutionHint() const { return HasExecutionHint; }
+
// Return true if the target has the load-and-trap facility.
bool hasLoadAndTrap() const { return HasLoadAndTrap; }
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt Mon Nov 28 08:01:51 2016
@@ -1883,3 +1883,67 @@
# CHECK: brcth %r15, 0x100000a9c
0xcc 0xf6 0x7f 0xff 0xff 0xff
+# 0x00000aa4:
+# CHECK: bpp 0, 0xaa4, 0
+0xc7 0x00 0x00 0x00 0x00 0x00
+
+# 0x00000aaa:
+# CHECK: bpp 14, 0xaaa, 4095(%r3)
+0xc7 0xe0 0x3f 0xff 0x00 0x00
+
+# 0x00000ab0:
+# CHECK: bpp 15, 0xab2, 0
+0xc7 0xf0 0x00 0x00 0x00 0x01
+
+# 0x00000ab6:
+# CHECK: bpp 0, 0xab4, 256(%r8)
+0xc7 0x00 0x81 0x00 0xff 0xff
+
+# 0x00000abc:
+# CHECK: bpp 14, 0xffffffffffff0abc, 0
+0xc7 0xe0 0x00 0x00 0x80 0x00
+
+# 0x00000ac2:
+# CHECK: bpp 15, 0x10ac0, 4095(%r7)
+0xc7 0xf0 0x7f 0xff 0x7f 0xff
+
+# 0x00000ac8:
+# CHECK: bprp 0, 0xac8, 0xac8
+0xc5 0x00 0x00 0x00 0x00 0x00
+
+# 0x00000ace:
+# CHECK: bprp 14, 0xace, 0xad0
+0xc5 0xe0 0x00 0x00 0x00 0x01
+
+# 0x00000ad4:
+# CHECK: bprp 15, 0xad4, 0xad2
+0xc5 0xf0 0x00 0xff 0xff 0xff
+
+# 0x00000ada:
+# CHECK: bprp 0, 0xada, 0xffffffffff000ada
+0xc5 0x00 0x00 0x80 0x00 0x00
+
+# 0x00000ae0:
+# CHECK: bprp 14, 0xae0, 0x1000ade
+0xc5 0xe0 0x00 0x7f 0xff 0xff
+
+# 0x00000ae6:
+# CHECK: bprp 14, 0xae8, 0xae6
+0xc5 0xe0 0x01 0x00 0x00 0x00
+
+# 0x00000aec:
+# CHECK: bprp 15, 0xaea, 0xaec
+0xc5 0xff 0xff 0x00 0x00 0x00
+
+# 0x00000af2:
+# CHECK: bprp 0, 0xfffffffffffffaf2, 0xaf2
+0xc5 0x08 0x00 0x00 0x00 0x00
+
+# 0x00000af8:
+# CHECK: bprp 14, 0x1af6, 0xaf8
+0xc5 0xe7 0xff 0x00 0x00 0x00
+
+# 0x00000afe:
+# CHECK: bprp 15, 0xcfe, 0x2afe
+0xc5 0xf1 0x00 0x00 0x10 0x00
+
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Mon Nov 28 08:01:51 2016
@@ -8008,6 +8008,18 @@
# CHECK: ny %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x54
+# CHECK: niai 0, 0
+0xb2 0xfa 0x00 0x00
+
+# CHECK: niai 15, 0
+0xb2 0xfa 0x00 0xf0
+
+# CHECK: niai 0, 15
+0xb2 0xfa 0x00 0x0f
+
+# CHECK: niai 15, 15
+0xb2 0xfa 0x00 0xff
+
# CHECK: ntstg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x25
Added: llvm/trunk/test/MC/SystemZ/fixups-zEC12.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/fixups-zEC12.s?rev=288031&view=auto
==============================================================================
--- llvm/trunk/test/MC/SystemZ/fixups-zEC12.s (added)
+++ llvm/trunk/test/MC/SystemZ/fixups-zEC12.s Mon Nov 28 08:01:51 2016
@@ -0,0 +1,34 @@
+
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=zEC12 --show-encoding %s | FileCheck %s
+
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=zEC12 -filetype=obj %s | \
+# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
+
+# CHECK: bpp 12, branch, 0 # encoding: [0xc7,0xc0,0x00,0x00,A,A]
+# CHECK: # fixup A - offset: 4, value: branch+4, kind: FK_390_PC16DBL
+# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_PC16DBL branch 0x4
+ .align 16
+ bpp 12, branch, 0
+
+# CHECK: bpp 12, branch at PLT, 0 # encoding: [0xc7,0xc0,0x00,0x00,A,A]
+# CHECK: # fixup A - offset: 4, value: branch at PLT+4, kind: FK_390_PC16DBL
+# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_PLT16DBL branch 0x4
+ .align 16
+ bpp 12, branch at plt, 0
+
+# CHECK: bprp 12, branch, target # encoding: [0xc5,0b1100AAAA,A,B,B,B]
+# CHECK-NEXT: # fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
+# CHECK-NEXT: # fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
+# CHECK-REL: 0x{{[0-9A-F]*1}} R_390_PC12DBL branch 0x1
+# CHECK-REL: 0x{{[0-9A-F]*3}} R_390_PC24DBL target 0x3
+ .align 16
+ bprp 12, branch, target
+
+# CHECK: bprp 12, branch at PLT, target at PLT # encoding: [0xc5,0b1100AAAA,A,B,B,B]
+# CHECK-NEXT: # fixup A - offset: 1, value: branch at PLT+1, kind: FK_390_PC12DBL
+# CHECK-NEXT: # fixup B - offset: 3, value: target at PLT+3, kind: FK_390_PC24DBL
+# CHECK-REL: 0x{{[0-9A-F]*1}} R_390_PLT12DBL branch 0x1
+# CHECK-REL: 0x{{[0-9A-F]*3}} R_390_PLT24DBL target 0x3
+ .align 16
+ bprp 12, branch at plt, target at plt
+
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-z196.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-z196.s?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-z196.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-z196.s Mon Nov 28 08:01:51 2016
@@ -34,6 +34,16 @@
aih %r0, (-1 << 31) - 1
aih %r0, (1 << 31)
+#CHECK: error: instruction requires: execution-hint
+#CHECK: bpp 0, 0, 0
+
+ bpp 0, 0, 0
+
+#CHECK: error: instruction requires: execution-hint
+#CHECK: bprp 0, 0, 0
+
+ bprp 0, 0, 0
+
#CHECK: error: offset out of range
#CHECK: brcth %r0, -0x1000000002
#CHECK: error: offset out of range
@@ -747,6 +757,11 @@
locr %r0,%r0,-1
locr %r0,%r0,16
+#CHECK: error: instruction requires: execution-hint
+#CHECK: niai 0, 0
+
+ niai 0, 0
+
#CHECK: error: instruction requires: transactional-execution
#CHECK: ntstg %r0, 524287(%r1,%r15)
Modified: llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad-zEC12.s Mon Nov 28 08:01:51 2016
@@ -5,6 +5,64 @@
# RUN: FileCheck < %t %s
#CHECK: error: invalid operand
+#CHECK: bpp -1, 0, 0
+#CHECK: error: invalid operand
+#CHECK: bpp 16, 0, 0
+#CHECK: error: offset out of range
+#CHECK: bpp 0, -0x10002, 0
+#CHECK: error: offset out of range
+#CHECK: bpp 0, -1, 0
+#CHECK: error: offset out of range
+#CHECK: bpp 0, 1, 0
+#CHECK: error: offset out of range
+#CHECK: bpp 0, 0x10000, 0
+#CHECK: error: invalid operand
+#CHECK: bpp 0, 0, -1
+#CHECK: error: invalid operand
+#CHECK: bpp 0, 0, 4096
+
+ bpp -1, 0, 0
+ bpp 16, 0, 0
+ bpp 0, -0x10002, 0
+ bpp 0, -1, 0
+ bpp 0, 1, 0
+ bpp 0, 0x10000, 0
+ bpp 0, 0, -1
+ bpp 0, 0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: bprp -1, 0, 0
+#CHECK: error: invalid operand
+#CHECK: bprp 16, 0, 0
+#CHECK: error: offset out of range
+#CHECK: bprp 0, -0x1002, 0
+#CHECK: error: offset out of range
+#CHECK: bprp 0, -1, 0
+#CHECK: error: offset out of range
+#CHECK: bprp 0, 1, 0
+#CHECK: error: offset out of range
+#CHECK: bprp 0, 0x1000, 0
+#CHECK: error: offset out of range
+#CHECK: bprp 0, 0, -0x1000002
+#CHECK: error: offset out of range
+#CHECK: bprp 0, 0, -1
+#CHECK: error: offset out of range
+#CHECK: bprp 0, 0, 1
+#CHECK: error: offset out of range
+#CHECK: bprp 0, 0, 0x1000000
+
+ bprp -1, 0, 0
+ bprp 16, 0, 0
+ bprp 0, -0x1002, 0
+ bprp 0, -1, 0
+ bprp 0, 1, 0
+ bprp 0, 0x1000, 0
+ bprp 0, 0, -0x1000002
+ bprp 0, 0, -1
+ bprp 0, 0, 1
+ bprp 0, 0, 0x1000000
+
+#CHECK: error: invalid operand
#CHECK: clt %r0, -1, 0
#CHECK: error: invalid operand
#CHECK: clt %r0, 16, 0
@@ -100,6 +158,20 @@
lcbb %r0, 0, 0
#CHECK: error: invalid operand
+#CHECK: niai -1, 0
+#CHECK: error: invalid operand
+#CHECK: niai 16, 0
+#CHECK: error: invalid operand
+#CHECK: niai 0, -1
+#CHECK: error: invalid operand
+#CHECK: niai 0, 16
+
+ niai -1, 0
+ niai 16, 0
+ niai 0, -1
+ niai 0, 16
+
+#CHECK: error: invalid operand
#CHECK: ntstg %r0, -524289
#CHECK: error: invalid operand
#CHECK: ntstg %r0, 524288
Modified: llvm/trunk/test/MC/SystemZ/insn-good-zEC12.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good-zEC12.s?rev=288031&r1=288030&r2=288031&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good-zEC12.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good-zEC12.s Mon Nov 28 08:01:51 2016
@@ -2,6 +2,118 @@
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch10 -show-encoding %s | FileCheck %s
+#CHECK: bpp 0, .[[LAB:L.*]]-65536, 0 # encoding: [0xc7,0x00,0x00,0x00,A,A]
+#CHECK: fixup A - offset: 4, value: (.[[LAB]]-65536)+4, kind: FK_390_PC16DBL
+ bpp 0, -0x10000, 0
+#CHECK: bpp 0, .[[LAB:L.*]]-2, 0 # encoding: [0xc7,0x00,0x00,0x00,A,A]
+#CHECK: fixup A - offset: 4, value: (.[[LAB]]-2)+4, kind: FK_390_PC16DBL
+ bpp 0, -2, 0
+#CHECK: bpp 0, .[[LAB:L.*]], 0 # encoding: [0xc7,0x00,0x00,0x00,A,A]
+#CHECK: fixup A - offset: 4, value: .[[LAB]]+4, kind: FK_390_PC16DBL
+ bpp 0, 0, 0
+#CHECK: bpp 0, .[[LAB:L.*]]+65534, 0 # encoding: [0xc7,0x00,0x00,0x00,A,A]
+#CHECK: fixup A - offset: 4, value: (.[[LAB]]+65534)+4, kind: FK_390_PC16DBL
+ bpp 0, 0xfffe, 0
+
+#CHECK: bpp 0, foo, 4095(%r3) # encoding: [0xc7,0x00,0x3f,0xff,A,A]
+#CHECK: fixup A - offset: 4, value: foo+4, kind: FK_390_PC16DBL
+#CHECK: bpp 15, foo, 1(%r11) # encoding: [0xc7,0xf0,0xb0,0x01,A,A]
+#CHECK: fixup A - offset: 4, value: foo+4, kind: FK_390_PC16DBL
+
+ bpp 0, foo, 4095(%r3)
+ bpp 15, foo, 1(%r11)
+
+#CHECK: bpp 3, bar+100, 4095 # encoding: [0xc7,0x30,0x0f,0xff,A,A]
+#CHECK: fixup A - offset: 4, value: (bar+100)+4, kind: FK_390_PC16DBL
+#CHECK: bpp 4, bar+100, 1 # encoding: [0xc7,0x40,0x00,0x01,A,A]
+#CHECK: fixup A - offset: 4, value: (bar+100)+4, kind: FK_390_PC16DBL
+
+ bpp 3, bar+100, 4095
+ bpp 4, bar+100, 1
+
+#CHECK: bpp 7, frob at PLT, 0 # encoding: [0xc7,0x70,0x00,0x00,A,A]
+#CHECK: fixup A - offset: 4, value: frob at PLT+4, kind: FK_390_PC16DBL
+#CHECK: bpp 8, frob at PLT, 0 # encoding: [0xc7,0x80,0x00,0x00,A,A]
+#CHECK: fixup A - offset: 4, value: frob at PLT+4, kind: FK_390_PC16DBL
+
+ bpp 7, frob at PLT, 0
+ bpp 8, frob at PLT, 0
+
+#CHECK: bprp 0, .[[LABA:L.*]]-4096, .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: (.[[LABA]]-4096)+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL
+ bprp 0, -0x1000, 0
+#CHECK: bprp 0, .[[LABA:L.*]]-2, .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: (.[[LABA]]-2)+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL
+ bprp 0, -2, 0
+#CHECK: bprp 0, .[[LABA:L.*]], .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL
+ bprp 0, 0, 0
+#CHECK: bprp 0, .[[LABA:L.*]]+4094, .[[LABB:L.*]] # encoding: [0xc5,0b0000AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: (.[[LABA]]+4094)+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL
+ bprp 0, 0xffe, 0
+#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]]-16777216 # encoding: [0xc5,0b1111AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: (.[[LABB]]-16777216)+3, kind: FK_390_PC24DBL
+ bprp 15, 0, -0x1000000
+#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]]-2 # encoding: [0xc5,0b1111AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: (.[[LABB]]-2)+3, kind: FK_390_PC24DBL
+ bprp 15, 0, -2
+#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]] # encoding: [0xc5,0b1111AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: .[[LABB]]+3, kind: FK_390_PC24DBL
+ bprp 15, 0, 0
+#CHECK: bprp 15, .[[LABA:L.*]], .[[LABB:L.*]]+16777214 # encoding: [0xc5,0b1111AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: .[[LABA]]+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: (.[[LABB]]+16777214)+3, kind: FK_390_PC24DBL
+ bprp 15, 0, 0xfffffe
+
+#CHECK: bprp 1, branch, target # encoding: [0xc5,0b0001AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
+#CHECK: bprp 2, branch, target # encoding: [0xc5,0b0010AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
+#CHECK: bprp 3, branch, target # encoding: [0xc5,0b0011AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
+
+ bprp 1, branch, target
+ bprp 2, branch, target
+ bprp 3, branch, target
+
+#CHECK: bprp 4, branch+100, target # encoding: [0xc5,0b0100AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: (branch+100)+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
+#CHECK: bprp 5, branch, target+100 # encoding: [0xc5,0b0101AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: (target+100)+3, kind: FK_390_PC24DBL
+#CHECK: bprp 6, branch+100, target+100 # encoding: [0xc5,0b0110AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: (branch+100)+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: (target+100)+3, kind: FK_390_PC24DBL
+
+ bprp 4, branch+100, target
+ bprp 5, branch, target+100
+ bprp 6, branch+100, target+100
+
+#CHECK: bprp 7, branch at PLT, target # encoding: [0xc5,0b0111AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch at PLT+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
+#CHECK: bprp 8, branch, target at PLT # encoding: [0xc5,0b1000AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target at PLT+3, kind: FK_390_PC24DBL
+#CHECK: bprp 9, branch at PLT, target at PLT # encoding: [0xc5,0b1001AAAA,A,B,B,B]
+#CHECK: fixup A - offset: 1, value: branch at PLT+1, kind: FK_390_PC12DBL
+#CHECK: fixup B - offset: 3, value: target at PLT+3, kind: FK_390_PC24DBL
+
+ bprp 7, branch at plt, target
+ bprp 8, branch, target at plt
+ bprp 9, branch at plt, target at plt
+
#CHECK: clt %r0, 12, -524288 # encoding: [0xeb,0x0c,0x00,0x00,0x80,0x23]
#CHECK: clt %r0, 12, -1 # encoding: [0xeb,0x0c,0x0f,0xff,0xff,0x23]
#CHECK: clt %r0, 12, 0 # encoding: [0xeb,0x0c,0x00,0x00,0x00,0x23]
@@ -184,6 +296,16 @@
etnd %r15
etnd %r7
+#CHECK: niai 0, 0 # encoding: [0xb2,0xfa,0x00,0x00]
+#CHECK: niai 15, 0 # encoding: [0xb2,0xfa,0x00,0xf0]
+#CHECK: niai 0, 15 # encoding: [0xb2,0xfa,0x00,0x0f]
+#CHECK: niai 15, 15 # encoding: [0xb2,0xfa,0x00,0xff]
+
+ niai 0, 0
+ niai 15, 0
+ niai 0, 15
+ niai 15, 15
+
#CHECK: ntstg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
#CHECK: ntstg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
#CHECK: ntstg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
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