[PATCH] D27144: [AVX-512] Correctly preserve the passthru semantics of the FMA scalar intrinsics

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: delena, zvi, v_klochkov.
craig.topper added a subscriber: llvm-commits.

Scalar intrinsics have specific semantics about the which input's upper bits are passed through to the output. The same input is also supposed to be the input we use for the lower element when the mask bit is 0 in a masked operation. We aren't currently keeping these semantics with instruction selection.

This patch corrects this by introducing new scalar FMA ISD nodes that indicate whether operand 1(one of the multiply inputs) or operand 3(the additon/subtraction input) should pass thru its upper bits.

We use this information to select 213/132 form for the operand 1 version and the 231 form for the operand 3 version.

We also use this information to suppress combining FNEG operations on the passthru input since semantically the passthru bits aren't negated. This is stronger than the earlier check added for a user being SELECTS so we can remove that.

This fixes PR30913.


https://reviews.llvm.org/D27144

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86IntrinsicsInfo.h
  test/CodeGen/X86/avx512-intrinsics.ll
  test/CodeGen/X86/fma-fneg-combine.ll

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