[PATCH] D27098: [ELF] Refactor EhOutputSection

[Eugene Leviant via llvm-commits]

evgeny777 created this revision.
evgeny777 added reviewers: ruiu, rafael.
evgeny777 added subscribers: grimar, ikudrin, llvm-commits.
evgeny777 set the repository for this revision to rL LLVM.
evgeny777 added a project: lld.

Brush up few functions + fancier error messages


Repository:
  rL LLVM

https://reviews.llvm.org/D27098

Files:
  ELF/OutputSections.cpp
  ELF/OutputSections.h


Index: ELF/OutputSections.h
===================================================================
--- ELF/OutputSections.h
+++ ELF/OutputSections.h
@@ -175,12 +175,10 @@
   void addSectionAux(EhInputSection<ELFT> *S, llvm::ArrayRef<RelTy> Rels);
 
   template <class RelTy>
-  CieRecord *addCie(EhSectionPiece &Piece, EhInputSection<ELFT> *Sec,
-                    ArrayRef<RelTy> Rels);
+  CieRecord *addCie(EhSectionPiece &Piece, ArrayRef<RelTy> Rels);
 
   template <class RelTy>
-  bool isFdeLive(EhSectionPiece &Piece, EhInputSection<ELFT> *Sec,
-                 ArrayRef<RelTy> Rels);
+  bool isFdeLive(EhSectionPiece &Piece, ArrayRef<RelTy> Rels);
 
   uintX_t getFdePc(uint8_t *Buf, size_t Off, uint8_t Enc);
 
Index: ELF/OutputSections.cpp
===================================================================
--- ELF/OutputSections.cpp
+++ ELF/OutputSections.cpp
@@ -273,11 +273,11 @@
 template <class ELFT>
 template <class RelTy>
 CieRecord *EhOutputSection<ELFT>::addCie(EhSectionPiece &Piece,
-                                         EhInputSection<ELFT> *Sec,
                                          ArrayRef<RelTy> Rels) {
+  EhInputSection<ELFT> *Sec = cast<EhInputSection<ELFT>>(Piece.ID);
   const endianness E = ELFT::TargetEndianness;
   if (read32<E>(Piece.data().data() + 4) != 0)
-    fatal("CIE expected at beginning of .eh_frame: " + Sec->Name);
+    fatal(toString(Sec) + ": CIE expected at beginning of .eh_frame");
 
   SymbolBody *Personality = nullptr;
   unsigned FirstRelI = Piece.FirstRelocation;
@@ -300,11 +300,11 @@
 template <class ELFT>
 template <class RelTy>
 bool EhOutputSection<ELFT>::isFdeLive(EhSectionPiece &Piece,
-                                      EhInputSection<ELFT> *Sec,
                                       ArrayRef<RelTy> Rels) {
+  EhInputSection<ELFT> *Sec = cast<EhInputSection<ELFT>>(Piece.ID);
   unsigned FirstRelI = Piece.FirstRelocation;
   if (FirstRelI == (unsigned)-1)
-    fatal("FDE doesn't reference another section");
+    fatal(toString(Sec) + ": FDE doesn't reference another section");
   const RelTy &Rel = Rels[FirstRelI];
   SymbolBody &B = Sec->getFile()->getRelocTargetSym(Rel);
   auto *D = dyn_cast<DefinedRegular<ELFT>>(&B);
@@ -333,16 +333,16 @@
     size_t Offset = Piece.InputOff;
     uint32_t ID = read32<E>(Piece.data().data() + 4);
     if (ID == 0) {
-      OffsetToCie[Offset] = addCie(Piece, Sec, Rels);
+      OffsetToCie[Offset] = addCie(Piece, Rels);
       continue;
     }
 
     uint32_t CieOffset = Offset + 4 - ID;
     CieRecord *Cie = OffsetToCie[CieOffset];
     if (!Cie)
-      fatal("invalid CIE reference");
+      fatal(toString(Sec) + ": invalid CIE reference");
 
-    if (!isFdeLive(Piece, Sec, Rels))
+    if (!isFdeLive(Piece, Rels))
       continue;
     Cie->FdePieces.push_back(&Piece);
     NumFdes++;


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