[PATCH] D27046: TableGen: Allow signed immediates for instruction aliases

[Jacob Baungard Hansen via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL287856: TableGen: Allow signed immediates for instruction aliases (authored by jacob_hansen).

Changed prior to commit:
  https://reviews.llvm.org/D27046?vs=79071&id=79190#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D27046

Files:
  llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp


Index: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
===================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
@@ -879,7 +879,7 @@
           IAP.addCond(Op + ".isImm()");
 
           Cond = Op + ".getImm() == " +
-                 llvm::utostr(CGA.ResultOperands[i].getImm());
+                 llvm::itostr(CGA.ResultOperands[i].getImm());
           IAP.addCond(Cond);
           break;
         }


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