[PATCH] D27057: AMDGPU: Fix adding extra implicit def of register

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl.

In the scalar case, there's no reason to add an additional def of the same register.


https://reviews.llvm.org/D27057

Files:
  lib/Target/AMDGPU/SIRegisterInfo.cpp


Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -476,16 +476,18 @@
       = MF->getMachineMemOperand(PInfo, MMO->getFlags(),
                                  EltSize, MinAlign(Align, EltSize * i));
 
-    BuildMI(*MBB, MI, DL, Desc)
+    auto MIB = BuildMI(*MBB, MI, DL, Desc)
       .addReg(SubReg, getDefRegState(!IsStore))
       .addReg(ScratchRsrcReg)
       .addReg(SOffset, SOffsetRegState)
       .addImm(Offset)
       .addImm(0) // glc
       .addImm(0) // slc
       .addImm(0) // tfe
-      .addMemOperand(NewMMO)
-      .addReg(ValueReg, RegState::Implicit | SrcDstRegState);
+      .addMemOperand(NewMMO);
+
+    if (NumSubRegs > 1)
+      MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
   }
 
   if (RanOutOfSGPRs) {


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