[PATCH] D27028: Add intrinsics for constrained floating point operations

[Hal Finkel via llvm-commits]

hfinkel added a comment.

> I intend to model the implicit uses and defs of FP control and status registers in a future revision, which should be sufficient to prevent unwanted optimizations at the MachineInstr level. There is also a potential for incorrect code motion in during instruction selection. My tentative plan to handle that is to introduce pseudo-instruction nodes that wrap the inputs and outputs of the FP operations created based on the new intrinsics and effectively model the implicit FP control and status register behavior and use a chain. These nodes would then be eliminated during instruction selection.

Based on our conversation at the dev meeting, here's how I thought this would work:

1. Introduce target-independent chain-carrying nodes to represent these operations. For argument's sake, STRICT_FADD, etc.
2. Since nothing in the SDAG knows about what these nodes do, there's no problem with optimizations doing bad things.
3. You'd do something minimal in SelectionDAGISel::DoInstructionSelection() around the call to:

  Select(Node);

so that it would become:

  bool IsStrictFPOp = isStrictFPOp(Node);
  if (IsStrictFPOp)
    mutateStrictFPToFP(Node); // STRICT_FADD -> FADD, etc.
  
  Select(Node);
  
  if (IsStrictFPOp && !TLI->addStrictFPRegDeps(Node))
    report_fatal_error("Could not add strict FP reg deps");

and then you'd be done. Obviously this is somewhat hand wavy, but if there are complexities I'm overlooking, I'd like to understand them.

      


Repository:
  rL LLVM

https://reviews.llvm.org/D27028