[llvm] r287681 - [mips] seb, seh instruction aliases
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 22 11:17:24 PST 2016
Author: sdardis
Date: Tue Nov 22 13:17:23 2016
New Revision: 287681
URL: http://llvm.org/viewvc/llvm-project?rev=287681&view=rev
Log:
[mips] seb, seh instruction aliases
Add the single operand form.
Reviewers: vkalintiris
Differential Revision: https://reviews.llvm.org/D26961
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Tue Nov 22 13:17:23 2016
@@ -1828,6 +1828,10 @@ def : MipsInstAlias<"xor $rs, $imm",
def : MipsInstAlias<"not $rt, $rs",
(NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
ISA_MICROMIPS32R6;
+def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MICROMIPS32R6;
+def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MICROMIPS32R6;
//===----------------------------------------------------------------------===//
//
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue Nov 22 13:17:23 2016
@@ -1183,4 +1183,8 @@ let Predicates = [InMicroMips] in {
(BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqz $rs,$offset",
(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
+ def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MIPS32R2_NOT_32R6_64R6;
+ def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MIPS32R2_NOT_32R6_64R6;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Nov 22 13:17:23 2016
@@ -2437,6 +2437,10 @@ let AdditionalPredicates = [NotInMicroMi
(SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"srl $rd, $rt",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+ def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MIPS32R2;
+ def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
+ ISA_MIPS32R2;
}
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync",
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Tue Nov 22 13:17:23 2016
@@ -120,7 +120,9 @@ msubu $4, $5 # CHECK: msu
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
+seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]
seh $9, $6 # CHECK: seh $9, $6 # encoding: [0x01,0x26,0x3b,0x3c]
+seh $9 # CHECK: seh $9, $9 # encoding: [0x01,0x29,0x3b,0x3c]
wsbh $9, $6 # CHECK: wsbh $9, $6 # encoding: [0x01,0x26,0x7b,0x3c]
ext $9, $6, 3, 7 # CHECK: ext $9, $6, 3, 7 # encoding: [0x01,0x26,0x30,0xec]
ins $9, $6, 3, 7 # CHECK: ins $9, $6, 3, 7 # encoding: [0x01,0x26,0x48,0xcc]
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue Nov 22 13:17:23 2016
@@ -111,7 +111,9 @@
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
sb16 $3, 4($16) # CHECK: sb16 $3, 4($16) # encoding: [0x89,0x84]
seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
+ seb $3 # CHECK: seb $3, $3 # encoding: [0x00,0x63,0x2b,0x3c]
seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x00,0x63,0x3b,0x3c]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80]
sh16 $4, 8($17) # CHECK: sh16 $4, 8($17) # encoding: [0xaa,0x14]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Tue Nov 22 13:17:23 2016
@@ -48,6 +48,10 @@ a:
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
+ seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
+ seb $3 # CHECK: seb $3, $3 # encoding: [0x00,0x63,0x2b,0x3c]
+ seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x00,0x63,0x3b,0x3c]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90]
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Tue Nov 22 13:17:23 2016
@@ -187,8 +187,10 @@ a:
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
- seb $25,$15
- seh $v1,$12
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Tue Nov 22 13:17:23 2016
@@ -187,8 +187,10 @@ a:
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
- seb $25,$15
- seh $v1,$12
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Tue Nov 22 13:17:23 2016
@@ -188,8 +188,10 @@ a:
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
- seb $25,$15
- seh $v1,$12
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Tue Nov 22 13:17:23 2016
@@ -195,6 +195,10 @@ a:
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Tue Nov 22 13:17:23 2016
@@ -260,8 +260,10 @@ a:
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
- seb $25,$15
- seh $v1,$12
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Tue Nov 22 13:17:23 2016
@@ -260,8 +260,10 @@ a:
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
- seb $25,$15
- seh $v1,$12
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sh $14,-6704($15)
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Tue Nov 22 13:17:23 2016
@@ -261,8 +261,10 @@ a:
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
- seb $25,$15
- seh $v1,$12
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=287681&r1=287680&r2=287681&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Tue Nov 22 13:17:23 2016
@@ -221,6 +221,10 @@ a:
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
+ seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
+ seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
+ seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
+ seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
More information about the llvm-commits
mailing list