[llvm] r287573 - [mips] seq macro support
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 21 12:30:41 PST 2016
Author: sdardis
Date: Mon Nov 21 14:30:41 2016
New Revision: 287573
URL: http://llvm.org/viewvc/llvm-project?rev=287573&view=rev
Log:
[mips] seq macro support
This patch adds the seq macro.
This partially resolves PR/30381.
Thanks to Sean Bruno for reporting the issue!
Reviewers: zoran.jovanovic, vkalintiris, seanbruno
Differential Revision: https://reviews.llvm.org/D24607
Added:
llvm/trunk/test/MC/Mips/macro-seq.s
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=287573&r1=287572&r2=287573&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Nov 21 14:30:41 2016
@@ -252,6 +252,12 @@ class MipsAsmParser : public MCTargetAsm
bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, bool IsLoad);
+ bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
+ bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
bool reportParseError(Twine ErrorMsg);
bool reportParseError(SMLoc Loc, Twine ErrorMsg);
@@ -2223,6 +2229,10 @@ MipsAsmParser::tryExpandInstruction(MCIn
Inst.getOpcode() == Mips::LDMacro)
? MER_Fail
: MER_Success;
+ case Mips::SEQMacro:
+ return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SEQIMacro:
+ return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
}
}
@@ -3915,6 +3925,85 @@ bool MipsAsmParser::expandLoadStoreDMacr
return false;
}
+bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+
+ warnIfNoMacro(IDLoc);
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ if (Inst.getOperand(1).getReg() != Mips::ZERO &&
+ Inst.getOperand(2).getReg() != Mips::ZERO) {
+ TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(),
+ Inst.getOperand(1).getReg(), Inst.getOperand(2).getReg(),
+ IDLoc, STI);
+ TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
+ Inst.getOperand(0).getReg(), 1, IDLoc, STI);
+ return false;
+ }
+
+ unsigned Reg = 0;
+ if (Inst.getOperand(1).getReg() == Mips::ZERO) {
+ Reg = Inst.getOperand(2).getReg();
+ } else {
+ Reg = Inst.getOperand(1).getReg();
+ }
+ TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), Reg, 1, IDLoc, STI);
+ return false;
+}
+
+bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+
+ warnIfNoMacro(IDLoc);
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ unsigned Opc;
+ int64_t Imm = Inst.getOperand(2).getImm();
+ unsigned Reg = Inst.getOperand(1).getReg();
+
+ if (Imm == 0) {
+ TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
+ Inst.getOperand(1).getReg(), 1, IDLoc, STI);
+ return false;
+ } else {
+
+ if (Reg == Mips::ZERO) {
+ Warning(IDLoc, "comparison is always false");
+ TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
+ Inst.getOperand(0).getReg(), Reg, Reg, IDLoc, STI);
+ return false;
+ }
+
+ if (Imm > -0x8000 && Imm < 0) {
+ Imm = -Imm;
+ Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
+ } else {
+ Opc = Mips::XORi;
+ }
+ }
+ if (!isUInt<16>(Imm)) {
+ unsigned ATReg = getATReg(IDLoc);
+ if (!ATReg)
+ return true;
+
+ if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
+ Out, STI))
+ return true;
+
+ TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(),
+ Inst.getOperand(1).getReg(), ATReg, IDLoc, STI);
+ TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
+ Inst.getOperand(0).getReg(), 1, IDLoc, STI);
+ return false;
+ }
+
+ TOut.emitRRI(Opc, Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(),
+ Imm, IDLoc, STI);
+ TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(),
+ Inst.getOperand(0).getReg(), 1, IDLoc, STI);
+ return false;
+}
+
unsigned
MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
const OperandVector &Operands) {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=287573&r1=287572&r2=287573&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Nov 21 14:30:41 2016
@@ -203,6 +203,8 @@ def InMips16Mode : Predicate<"Subtarg
AssemblerPredicate<"FeatureMips16">;
def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
AssemblerPredicate<"FeatureCnMips">;
+def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
+ AssemblerPredicate<"!FeatureCnMips">;
def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;
def RelocPIC : Predicate<"TM.isPositionIndependent()">;
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
@@ -335,6 +337,10 @@ class ASE_CNMIPS {
list<Predicate> InsnPredicates = [HasCnMips];
}
+class NOT_ASE_CNMIPS {
+ list<Predicate> InsnPredicates = [NotCnMips];
+}
+
class ASE_MIPS64_CNMIPS {
list<Predicate> InsnPredicates = [HasMips64, HasCnMips];
}
@@ -2260,6 +2266,21 @@ def : MipsInstAlias<"dror $rd, $imm",
def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
"abs\t$rd, $rs">;
+def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+ "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS;
+
+def : MipsInstAlias<"seq $rd, $rs",
+ (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
+ NOT_ASE_CNMIPS;
+
+def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, simm32_relaxed:$imm),
+ "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS;
+
+def : MipsInstAlias<"seq $rd, $imm",
+ (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,
+ NOT_ASE_CNMIPS;
//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/Mips/macro-seq.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-seq.s?rev=287573&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-seq.s (added)
+++ llvm/trunk/test/MC/Mips/macro-seq.s Mon Nov 21 14:30:41 2016
@@ -0,0 +1,52 @@
+# RUN: llvm-mc -arch=mips -mcpu=mips1 < %s | FileCheck --check-prefixes=ALL,MIPS32 %s
+# RUN: llvm-mc -arch=mips -mcpu=mips64 < %s | FileCheck --check-prefixes=ALL,MIPS64 %s
+
+# ALL: .text
+seq $2, $11, $0
+# ALL: sltiu $2, $11, 1
+seq $2, $0, $11
+# ALL: sltiu $2, $11, 1
+seq $2, $0, $0
+# ALL: sltiu $2, $zero, 1
+seq $2, $11, $12
+# ALL: xor $2, $11, $12
+# ALL: sltiu $2, $2, 1
+seq $2, $11, 45
+# ALL: xori $2, $11, 45
+seq $2, $12, 0x76666
+# ALL: lui $1, 7
+# ALL: ori $1, $1, 26214
+# ALL: xor $2, $12, $1
+# ALL: sltiu $2, $2, 1
+seq $2, $3
+# ALL: xor $2, $2, $3
+# ALL: sltiu $2, $2, 1
+seq $2, 0x8888
+# ALL: xori $2, $2, 34952
+# ALL: sltiu $2, $2, 1
+seq $2, $3, -1546
+# MIPS32: addiu $2, $3, 1546
+# MIPS64: daddiu $2, $3, 1546
+# ALL: sltiu $2, $2, 1
+seq $2, -7546
+# MIPS32: addiu $2, $2, 7546
+# MIPS64: daddiu $2, $2, 7546
+# ALL: sltiu $2, $2, 1
+seq $4, $5, -66666
+# ALL: lui $1, 65534
+# ALL: ori $1, $1, 64406
+# ALL: xor $4, $5, $1
+# ALL: sltiu $4, $4, 1
+seq $4, $5, -2147483648
+# ALL: lui $1, 32768
+# ALL: xor $4, $5, $1
+# ALL: sltiu $4, $4, 1
+seq $4, -2147483648
+# ALL: lui $1, 32768
+# ALL: xor $4, $4, $1
+# ALL: sltiu $4, $4, 1
+seq $4, $5, 0
+# ALL: sltiu $4, $5, 1
+seq $4, $zero, 1
+# MIPS32: move $4, $zero
+# MIPS64: daddu $4, $zero, $zero
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