[llvm] r287500 - Some instructions were missing, other implemented falsely. this patch aims at amending those issues. full list:
Coby Tayree via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 20 09:09:56 PST 2016
Author: coby
Date: Sun Nov 20 11:09:56 2016
New Revision: 287500
URL: http://llvm.org/viewvc/llvm-project?rev=287500&view=rev
Log:
Some instructions were missing, other implemented falsely. this patch aims at amending those issues. full list:
vcvtps2pd
vcvtudq2pd
vcvtps2qq
vcvttps2qq
vcvtps2uqq
vcvttps2uqq
variants are:
[Dst]XMM(zero-masked/merge-masked/unmasked)
[Src]Mem64
Differential Revision: https://reviews.llvm.org/D26799
Added:
llvm/trunk/test/MC/X86/intel-syntax-x86-avx512dq_vl.s
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=287500&r1=287499&r2=287500&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Nov 20 11:09:56 2016
@@ -6096,14 +6096,14 @@ def : Pat<(f32 (fpround FR64X:$src)),
multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
X86VectorVTInfo _Src, SDNode OpNode,
string Broadcast = _.BroadcastStr,
- string Alias = ""> {
+ string Alias = "", X86MemOperand MemOp = _Src.MemOp> {
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _Src.RC:$src), OpcodeStr, "$src", "$src",
(_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
- (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
+ (ins MemOp:$src), OpcodeStr#Alias, "$src", "$src",
(_.VT (OpNode (_Src.VT
(bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
@@ -6144,7 +6144,7 @@ multiclass avx512_cvtps2pd<bits<8> opc,
}
let Predicates = [HasVLX] in {
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
- X86vfpext, "{1to2}">, EVEX_V128;
+ X86vfpext, "{1to2}", "", f64mem>, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fpextend>,
EVEX_V256;
}
@@ -6203,7 +6203,7 @@ multiclass avx512_cvtdq2pd<bits<8> opc,
let Predicates = [HasVLX] in {
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
- OpNode128, "{1to2}">, EVEX_V128;
+ OpNode128, "{1to2}", "", i64mem>, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
EVEX_V256;
}
@@ -6375,7 +6375,7 @@ multiclass avx512_cvtps2qq<bits<8> opc,
// Explicitly specified broadcast string, since we take only 2 elements
// from v4f32x_info source
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
- "{1to2}">, EVEX_V128;
+ "{1to2}", "", f64mem>, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
EVEX_V256;
}
@@ -6393,7 +6393,7 @@ multiclass avx512_cvttps2qq<bits<8> opc,
// Explicitly specified broadcast string, since we take only 2 elements
// from v4f32x_info source
defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
- "{1to2}">, EVEX_V128;
+ "{1to2}", "", f64mem>, EVEX_V128;
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
EVEX_V256;
}
@@ -6428,8 +6428,8 @@ multiclass avx512_cvtqq2ps<bits<8> opc,
}
}
-defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
- EVEX_CD8<32, CD8VH>;
+defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>,
+ XS, EVEX_CD8<32, CD8VH>;
defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
X86VSintToFpRnd>,
Modified: llvm/trunk/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s?rev=287500&r1=287499&r2=287500&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s Sun Nov 20 11:09:56 2016
@@ -1343,3 +1343,32 @@
// CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax]
// CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00]
vcvtuqq2psy xmm16, ymmword ptr [rax]
+
+// CHECK: vcvtps2pd xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7c,0x8a,0x5a,0x49,0x10]
+ vcvtps2pd xmm1 {k2} {z}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtps2pd xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7c,0x0a,0x5a,0x49,0x10]
+ vcvtps2pd xmm1 {k2}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtudq2pd xmm2 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x8a,0x7a,0x51,0x10]
+ vcvtudq2pd xmm2 {k2} {z}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtudq2pd xmm2 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x0a,0x7a,0x51,0x10]
+ vcvtudq2pd xmm2 {k2}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtudq2pd xmm2, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x7a,0x51,0x10]
+ vcvtudq2pd xmm2, qword ptr [rcx+0x80]
+
+// CHECK: vcvtdq2pd xmm2 {k1}, qword ptr [rcx]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x09,0xe6,0x11]
+ vcvtdq2pd xmm2 {k1}, qword ptr [rcx]
+
+// CHECK: vcvtdq2pd xmm2 {k1} {z}, qword ptr [rcx]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x89,0xe6,0x11]
+ vcvtdq2pd xmm2 {k1} {z}, qword ptr [rcx]
+
Added: llvm/trunk/test/MC/X86/intel-syntax-x86-avx512dq_vl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-x86-avx512dq_vl.s?rev=287500&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax-x86-avx512dq_vl.s (added)
+++ llvm/trunk/test/MC/X86/intel-syntax-x86-avx512dq_vl.s Sun Nov 20 11:09:56 2016
@@ -0,0 +1,98 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl -mattr=+avx512dq -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10]
+ vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10]
+ vcvtps2qq xmm2 {k2}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvtps2qq xmm2, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10]
+ vcvtps2qq xmm2, qword ptr [rcx + 0x80]
+
+// CHECK: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10]
+ vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10]
+ vcvttps2qq xmm1 {k2}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvttps2qq xmm1, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10]
+ vcvttps2qq xmm1, qword ptr [rcx + 0x80]
+
+// CHECK: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10]
+ vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+
+// CHECK: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10]
+ vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+
+// CHECK: vcvtps2uqq xmm1, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10]
+ vcvtps2uqq xmm1, qword ptr [rcx + 128]
+
+// CHECK: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10]
+ vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+
+// CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10]
+ vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+
+// CHECK: vcvttps2uqq xmm1, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10]
+ vcvttps2uqq xmm1, qword ptr [rcx + 128]
+// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl -mattr=+avx512dq -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10]
+ vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10]
+ vcvtps2qq xmm2 {k2}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvtps2qq xmm2, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10]
+ vcvtps2qq xmm2, qword ptr [rcx + 0x80]
+
+// CHECK: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10]
+ vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10]
+ vcvttps2qq xmm1 {k2}, qword ptr [rcx + 0x80]
+
+// CHECK: vcvttps2qq xmm1, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10]
+ vcvttps2qq xmm1, qword ptr [rcx + 0x80]
+
+// CHECK: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10]
+ vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+
+// CHECK: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10]
+ vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+
+// CHECK: vcvtps2uqq xmm1, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10]
+ vcvtps2uqq xmm1, qword ptr [rcx + 128]
+
+// CHECK: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10]
+ vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+
+// CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10]
+ vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+
+// CHECK: vcvttps2uqq xmm1, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10]
+ vcvttps2uqq xmm1, qword ptr [rcx + 128]
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