[PATCH] D26874: AMDGPU: Remove m0 spilling code
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 18 15:21:09 PST 2016
arsenm created this revision.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl.
Since m0 isn't allocatable it should never be spilled anymore.
https://reviews.llvm.org/D26874
Files:
lib/Target/AMDGPU/SIRegisterInfo.cpp
Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -497,26 +497,15 @@
bool SpillToSMEM = ST.hasScalarStores() && EnableSpillSGPRToSMEM;
+ assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
+
// SubReg carries the "Kill" flag when SubReg == SuperReg.
unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned SubReg = NumSubRegs == 1 ?
SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));
if (SpillToSMEM) {
- if (SuperReg == AMDGPU::M0) {
- assert(NumSubRegs == 1);
- unsigned CopyM0
- = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
-
- BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), CopyM0)
- .addReg(AMDGPU::M0, getKillRegState(IsKill));
-
- // The real spill now kills the temp copy.
- SubReg = SuperReg = CopyM0;
- IsKill = true;
- }
-
int64_t FrOffset = FrameInfo.getObjectOffset(Index);
unsigned Size = FrameInfo.getObjectSize(Index);
unsigned Align = FrameInfo.getObjectAlignment(Index);
@@ -555,18 +544,6 @@
struct SIMachineFunctionInfo::SpilledReg Spill =
MFI->getSpilledReg(MF, Index, i);
if (Spill.hasReg()) {
- if (SuperReg == AMDGPU::M0) {
- assert(NumSubRegs == 1);
- unsigned CopyM0
- = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
- BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), CopyM0)
- .addReg(SuperReg, getKillRegState(IsKill));
-
- // The real spill now kills the temp copy.
- SubReg = SuperReg = CopyM0;
- IsKill = true;
- }
-
BuildMI(*MBB, MI, DL,
TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
Spill.VGPR)
@@ -634,13 +611,7 @@
unsigned SuperReg = MI->getOperand(0).getReg();
bool SpillToSMEM = ST.hasScalarStores() && EnableSpillSGPRToSMEM;
- // m0 is not allowed as with readlane/writelane, so a temporary SGPR and
- // extra copy is needed.
- bool IsM0 = (SuperReg == AMDGPU::M0);
- if (IsM0) {
- assert(NumSubRegs == 1);
- SuperReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
- }
+ assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
int64_t FrOffset = FrameInfo.getObjectOffset(Index);
@@ -717,11 +688,6 @@
}
}
- if (IsM0 && SuperReg != AMDGPU::M0) {
- BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
- .addReg(SuperReg);
- }
-
MI->eraseFromParent();
}
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