[llvm] r286912 - AMDGPU: Fix formatting of 1/2pi immediate
Nicolai Hähnle via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 18 07:32:29 PST 2016
Hi Matt,
Sorry that I didn't notice this earlier, but this change is incorrect:
when you feed the output of llvm-mc into itself, you get
test/MC/AMDGPU/literals.s:463:23: error: invalid operand for instruction
s_mov_b64_e32 s[0:1], 0.15915494
I'd suggest to print out the full 0.159154943091895317852646485335
instead, and perhaps refactor the test so that it calls llvm-mc twice in
a pipe to avoid problems like this in the future. This requires the test
to be split into valid and invalid parts.
Cheers,
Nicolai
On 15.11.2016 01:04, Matt Arsenault via llvm-commits wrote:
> Author: arsenm
> Date: Mon Nov 14 18:04:33 2016
> New Revision: 286912
>
> URL: http://llvm.org/viewvc/llvm-project?rev=286912&view=rev
> Log:
> AMDGPU: Fix formatting of 1/2pi immediate
>
> Modified:
> llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
> llvm/trunk/test/CodeGen/AMDGPU/imm.ll
> llvm/trunk/test/CodeGen/AMDGPU/llvm.cos.f16.ll
> llvm/trunk/test/CodeGen/AMDGPU/llvm.sin.f16.ll
> llvm/trunk/test/MC/AMDGPU/literals.s
>
> Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=286912&r1=286911&r2=286912&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Mon Nov 14 18:04:33 2016
> @@ -351,7 +351,7 @@ void AMDGPUInstPrinter::printImmediate32
> O << "-4.0";
> else if (Imm == 0x3e22f983 &&
> STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
> - O << "1/2pi";
> + O << "0.15915494";
> else
> O << formatHex(static_cast<uint64_t>(Imm));
> }
> @@ -385,7 +385,7 @@ void AMDGPUInstPrinter::printImmediate64
> O << "-4.0";
> else if (Imm == 0x3fc45f306dc9c882 &&
> STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
> - O << "1/2pi";
> + O << "0.15915494";
> else {
> assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
>
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/imm.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/imm.ll?rev=286912&r1=286911&r2=286912&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/imm.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/imm.ll Mon Nov 14 18:04:33 2016
> @@ -121,7 +121,7 @@ define void @store_inline_imm_m_4.0_f32(
>
> ; GCN-LABEL: {{^}}store_inline_imm_inv_2pi_f32:
> ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e22f983{{$}}
> -; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 1/2pi{{$}}
> +; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0.15915494{{$}}
> ; GCN: buffer_store_dword [[REG]]
> define void @store_inline_imm_inv_2pi_f32(float addrspace(1)* %out) {
> store float 0x3FC45F3060000000, float addrspace(1)* %out
> @@ -443,7 +443,7 @@ define void @add_inline_imm_neg_4.0_f64(
> ; SI: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
>
> ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
> -; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1/2pi
> +; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.15915494{{$}}
> ; VI: buffer_store_dwordx2 [[REG]]
> define void @add_inline_imm_inv_2pi_f64(double addrspace(1)* %out, double %x) {
> %y = fadd double %x, 0x3fc45f306dc9c882
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.cos.f16.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.cos.f16.ll?rev=286912&r1=286911&r2=286912&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.cos.f16.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.cos.f16.ll Mon Nov 14 18:04:33 2016
> @@ -7,7 +7,7 @@ declare <2 x half> @llvm.cos.v2f16(<2 x
> ; GCN-LABEL: {{^}}cos_f16
> ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
> ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
> -; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{1/2pi|0x3e22f983}}, v[[A_F32]]
> +; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]]
> ; GCN: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]]
> ; GCN: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]]
> ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
> @@ -30,10 +30,10 @@ entry:
> ; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
> ; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
> ; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], v[[HALF_PIE]], v[[A_F32_0]]
> -; VI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 1/2pi, v[[A_F32_0]]
> +; VI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]]
> ; GCN: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]]
> ; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], v[[HALF_PIE]], v[[A_F32_1]]
> -; VI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 1/2pi, v[[A_F32_1]]
> +; VI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]]
> ; GCN: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]]
> ; GCN: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]]
> ; GCN: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]]
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.sin.f16.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.sin.f16.ll?rev=286912&r1=286911&r2=286912&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/llvm.sin.f16.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/llvm.sin.f16.ll Mon Nov 14 18:04:33 2016
> @@ -7,7 +7,7 @@ declare <2 x half> @llvm.sin.v2f16(<2 x
> ; GCN-LABEL: {{^}}sin_f16
> ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
> ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
> -; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{1/2pi|0x3e22f983}}, v[[A_F32]]
> +; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]]
> ; GCN: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]]
> ; GCN: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]]
> ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
> @@ -30,10 +30,10 @@ entry:
> ; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
> ; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
> ; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], v[[HALF_PIE]], v[[A_F32_0]]
> -; VI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 1/2pi, v[[A_F32_0]]
> +; VI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]]
> ; GCN: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]]
> ; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], v[[HALF_PIE]], v[[A_F32_1]]
> -; VI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 1/2pi, v[[A_F32_1]]
> +; VI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]]
> ; GCN: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]]
> ; GCN: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]]
> ; GCN: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]]
>
> Modified: llvm/trunk/test/MC/AMDGPU/literals.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/literals.s?rev=286912&r1=286911&r2=286912&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/AMDGPU/literals.s (original)
> +++ llvm/trunk/test/MC/AMDGPU/literals.s Mon Nov 14 18:04:33 2016
> @@ -1,10 +1,10 @@
> // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
> -// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
> +// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
> // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
> // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
>
> // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
> -// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
> +// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
> // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
> // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
>
> @@ -429,11 +429,11 @@ v_and_b32_e32 v0, 0xffffffffffffffff, v1
> v_trunc_f32_e32 v0, 0x3fc45f306dc9c882
>
> // NOSICI: error: invalid operand for instruction
> -// VI: v_fract_f64_e32 v[0:1], 1/2pi ; encoding: [0xf8,0x64,0x00,0x7e]
> +// VI: v_fract_f64_e32 v[0:1], 0.15915494 ; encoding: [0xf8,0x64,0x00,0x7e]
> v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882
>
> // SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
> -// VI: v_trunc_f32_e32 v0, 1/2pi ; encoding: [0xf8,0x38,0x00,0x7e]
> +// VI: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e]
> v_trunc_f32_e32 v0, 0x3e22f983
>
> // SICI: v_fract_f64_e32 v[0:1], 0x3e22f983 ; encoding: [0xff,0x7c,0x00,0x7e,0x83,0xf9,0x22,0x3e]
> @@ -445,11 +445,11 @@ v_fract_f64_e32 v[0:1], 0x3e22f983
> v_trunc_f32_e64 v0, 0x3fc45f306dc9c882
>
> // NOSICI: error: invalid operand for instruction
> -// VI: v_fract_f64_e64 v[0:1], 1/2pi ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
> +// VI: v_fract_f64_e64 v[0:1], 0.15915494 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
> v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882
>
> // NOSICI: error: invalid operand for instruction
> -// VI: v_trunc_f32_e64 v0, 1/2pi ; encoding: [0x00,0x00,0x5c,0xd1,0xf8,0x00,0x00,0x00]
> +// VI: v_trunc_f32_e64 v0, 0.15915494 ; encoding: [0x00,0x00,0x5c,0xd1,0xf8,0x00,0x00,0x00]
> v_trunc_f32_e64 v0, 0x3e22f983
>
> // NOSICI: error: invalid operand for instruction
> @@ -457,21 +457,21 @@ v_trunc_f32_e64 v0, 0x3e22f983
> v_fract_f64_e64 v[0:1], 0x3e22f983
>
> // NOSICI: error: invalid operand for instruction
> -// VI: s_mov_b64 s[0:1], 1/2pi ; encoding: [0xf8,0x01,0x80,0xbe]
> +// VI: s_mov_b64 s[0:1], 0.15915494 ; encoding: [0xf8,0x01,0x80,0xbe]
> s_mov_b64_e32 s[0:1], 0.159154943091895317852646485335
>
> // SICI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xff,0x02,0x00,0x36,0x83,0xf9,0x22,0x3e]
> -// VI: v_and_b32_e32 v0, 1/2pi, v1 ; encoding: [0xf8,0x02,0x00,0x26]
> +// VI: v_and_b32_e32 v0, 0.15915494, v1 ; encoding: [0xf8,0x02,0x00,0x26]
> v_and_b32_e32 v0, 0.159154943091895317852646485335, v1
>
> // NOSICI: error: invalid operand for instruction
> -// VI: v_and_b32_e64 v0, 1/2pi, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf8,0x02,0x02,0x00]
> +// VI: v_and_b32_e64 v0, 0.15915494, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf8,0x02,0x02,0x00]
> v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
>
> // SICI: v_fract_f64_e32 v[0:1], 0x3fc45f30 ; encoding: [0xff,0x7c,0x00,0x7e,0x30,0x5f,0xc4,0x3f]
> -// VI: v_fract_f64_e32 v[0:1], 1/2pi ; encoding: [0xf8,0x64,0x00,0x7e]
> +// VI: v_fract_f64_e32 v[0:1], 0.15915494 ; encoding: [0xf8,0x64,0x00,0x7e]
> v_fract_f64 v[0:1], 0.159154943091895317852646485335
>
> // SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
> -// VI: v_trunc_f32_e32 v0, 1/2pi ; encoding: [0xf8,0x38,0x00,0x7e]
> +// VI: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e]
> v_trunc_f32 v0, 0.159154943091895317852646485335
>
>
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